Patents by Inventor Tsai-An Yu

Tsai-An Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TWO-IN-ONE MATTRESS WITH AIR MATTRESS AND MEMORY FOAM FOR PATIENT CARE
    Publication number: 20190116987
    Abstract: A mattress, bed, cushion, or other device to support a user in a pre-determined posture. The mattress, bed, cushion, or other device includes compressible cells configured to inflate based on characteristics of particular contact areas of the user, and contact, in response to inflating based on the characteristics, the user in various contact areas to support the pre-determined posture. In particular, inflating the compressible cells based on characteristics of particular contact areas reduces the risk of the user developing pressure ulcers.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 25, 2019
    Applicant: MedicusTek, Inc.
    Inventors: Aaron R. Clousing, Chia-Ming Hsu, Tsai-Yu Lin
  • SEMICONDUCTOR STRUCTURE WITH DOPED FIN-SHAPED STRUCTURES AND METHOD OF FABRICATING THE SAME
    Publication number: 20190067477
    Abstract: A semiconductor structure includes a substrate, fin-shaped structures disposed on the substrate, an isolation layer disposed between the fin-shaped structures, and a doped region disposed in an upper portion of the isolation layer, where the doped region is doped with helium or neon.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Shi-You Liu, Ming-Shiou Hsieh, Rong-Sin Lin, Han-Ting Yen, Tsai-Yu Wen, Ching-I Li
  • ANTIFUSE DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20190057754
    Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.
    Type: Application
    Filed: July 4, 2018
    Publication date: February 21, 2019
    Inventors: Tsai-Yu Huang, Pin-Yao Wang
  • TEST KEY LAYOUT AND METHOD OF MONITORING PATTERN MISALIGNMENTS USING TEST KEYS
    Publication number: 20190051567
    Abstract: A set of test key layout including multiple test keys and method of monitoring layout pattern misalignments using the test keys is provided. Each test key is composed of a testing electrode, an operating voltage (Vdd) line and a grounding voltage (Vss) line, wherein the patterns of test keys are defined by an overlapped portion of a first exposure pattern and a second exposure pattern, and the position of testing electrode is shifted sequentially in one direction in order of the test keys.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 14, 2019
    Inventor: Tsai-Yu Huang
  • Electronic assembly
    Patent number: 10180738
    Abstract: An electronic assembly including an electronic device and a stylus is provided. The electronic device includes a housing having a receiving groove and an opening, the opening communicating with the receiving groove, and a first connecting element disposed around the opening. The stylus includes a sleeve and a pen rod. The sleeve has a second connecting element and corresponds to the receiving groove. The second connecting element is combined with the first connecting element to fix the sleeve to the housing. The pen rod is slidably disposed in the sleeve and has a first end and a second end opposite to each other, and a third connecting element located at the first end.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 15, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jyh-Chyang Tzou, Tsai-Yu Lin, Hsin Yeh, Wei-Hao Lan
  • Memory cell with a read selection transistor and a program selection transistor
    Patent number: 10141035
    Abstract: The memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor. The read selection transistor has a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 27, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsai-Yu Huang, Pin-Yao Wang
  • POLARIZING PLATE WITH OPTICAL COMPENSATION FUNCTION
    Publication number: 20180313989
    Abstract: A polarizing plate with optical compensation function is provided. The polarizing plate includes a polarizer, a liquid crystal optical compensation film, a first adhesive layer, an adhesion-promoting layer, a protective film, and a second adhesive layer. The liquid crystal optical compensation film is disposed on one side of the polarizer. The first adhesive layer is disposed between the polarizer and the liquid crystal optical compensation film. The adhesion-promoting layer is disposed between the first adhesive layer and the liquid crystal optical compensation film. The protective film is disposed on one side of the polarizer relative to the liquid crystal optical compensation film. The second adhesive layer is disposed between the polarizer and the protective film.
    Type: Application
    Filed: January 11, 2018
    Publication date: November 1, 2018
    Applicant: Imat Corporation
    Inventors: Tsai-An Yu, Da-Ren Chiou, Shih-Ming Hung, Kuo-Chen Wu, Yi-Chien Chen
  • ELECTRONIC ASSEMBLY
    Publication number: 20180275780
    Abstract: An electronic assembly including an electronic device and a stylus is provided. The electronic device includes a housing having a receiving groove and an opening, the opening communicating with the receiving groove, and a first connecting element disposed around the opening. The stylus includes a sleeve and a pen rod. The sleeve has a second connecting element and corresponds to the receiving groove. The second connecting element is combined with the first connecting element to fix the sleeve to the housing. The pen rod is slidably disposed in the sleeve and has a first end and a second end opposite to each other, and a third connecting element located at the first end.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 27, 2018
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Jyh-Chyang Tzou, Tsai-Yu Lin, Hsin Yeh, Wei-Hao Lan
  • Electronic device having stand
    Patent number: 10037050
    Abstract: An electronic device includes a body, a stand and a sliding member. The stand is rotatably connected to the body. The sliding member is slidably disposed on the body and has at least one stopping portion and at least one pushing portion. When the sliding member is located at a first position, the stopping portion interferes with the stand to stop the stand from expanding from the body. When the sliding member slides relative to the body to be away from the first position, the stopping portion releases the stand and the pushing portion pushes the stand to drive the stand to rotate and expand from the body.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 31, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chia-Chi Lin, Wei-Hao Lan, Tsai-Yu Lin, Jyh-Chyang Tzou, Hsin Yeh, Tzu-Fang Huang
  • Constructions comprising rutile-type titanium oxide; and methods of forming and utilizing rutile-type titanium oxide
    Patent number: 10008381
    Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris M. Carlson, Vassil N. Antonov
  • METHOD FOR MANUFACTURING FINS
    Publication number: 20180108570
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Application
    Filed: November 19, 2017
    Publication date: April 19, 2018
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Method for manufacturing fins
    Patent number: 9947588
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Grant
    Filed: November 19, 2017
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Pivot structure and electronic device having the same
    Patent number: 9946301
    Abstract: A pivot structure includes a base, a bracket, an elastic component, and a positioning assembly. The bracket is rotatably connected to the base. The elastic component is disposed on the base. The positioning assembly includes an elastic clip and a pillar. The elastic clip is pivoted to the base and has a first releasing segment and a first positioning segment. The pillar is connected to the bracket and has a second positioning segment. The pillar is rotatably clipped in the elastic clip. The bracket is adapted to be expanded to a first expanding state through an elastic force of the elastic component, so as to drive the second positioning segment to move along the first releasing segment. The bracket is adapted to receive an external force to be further expanded to a second expanding state, so as to drive the second positioning segment to move to the first positioning segment.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 17, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Hao Lan, Jyh-Chyang Tzou, Ching-Tai Chang, Chia-Chi Lin, Tsai-Yu Lin, Hsin Yeh, Che-Hsien Lin, Cheng-Shiue Jan
  • SEMICONDUCTOR DEVICE
    Publication number: 20180083141
    Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 22, 2018
    Inventors: Shih-Cheng Chen, Tsai-Yu Wen, Shan Ye, Tsuo-Wen Lu
  • ELECTRONIC DEVICE HAVING STAND
    Publication number: 20180052487
    Abstract: An electronic device includes a body, a stand and a sliding member. The stand is rotatably connected to the body. The sliding member is slidably disposed on the body and has at least one stopping portion and at least one pushing portion. When the sliding member is located at a first position, the stopping portion interferes with the stand to stop the stand from expanding from the body. When the sliding member slides relative to the body to be away from the first position, the stopping portion releases the stand and the pushing portion pushes the stand to drive the stand to rotate and expand from the body.
    Type: Application
    Filed: July 4, 2017
    Publication date: February 22, 2018
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chia-Chi Lin, Wei-Hao Lan, Tsai-Yu Lin, Jyh-Chyang Tzou, Hsin Yeh, Tzu-Fang Huang
  • Electronic apparatus having a base
    Patent number: 9898038
    Abstract: An electronic apparatus includes a base and an electronic device. The base includes a first main body and at least one first connection portion. The first connection portion includes a rotating component, and the rotating component is pivoted to the first main body and has a driven portion and a positioning portion. The electronic device includes a second main body and at least one second connection portion. The second connection portion includes an elastic component and a positioning trench. The elastic component is connected to the second main body, and the positioning trench is formed on the second main body. When the base supports the electronic device so that the first connection portion is aligned to the second connection portion, the elastic component pushes the driven portion such that the positioning portion is engaged into the positioning trench.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 20, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jyh-Chyang Tzou, Hsin Yeh, Chia-Shin Weng, Wei-Hao Lan, Tsai-Yu Lin, Yuan-Ping Chu
  • Method for manufacturing transistor with SiCN/SiOCN multilayer spacer
    Patent number: 9882022
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • ULTRA-THIN BROADBAND RETARDATION FILM
    Publication number: 20180017723
    Abstract: An ultra-thin broadband retardation film is provided. The broadband retardation film includes a first retardation film and a second retardation film. The second retardation film is disposed on a side of the first retardation film, wherein an in-plane retardation value Ro of the first retardation film is between 70 nm and 130 nm, an in-plane retardation value Ro of the second retardation film is between 140 nm and 260 nm, and an angle between an optic axis of the first retardation film and an optic axis of the second retardation film is between 35° and 70°.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 18, 2018
    Applicant: imat corporation
    Inventors: Tsai-An Yu, Da-Ren Chiou, Shih-Ming Hung, Peng-Shun Tsai, Yi-Ting Chiu, Kuo-Chen Wu, Yi-Chien Chen
  • Stylus
    Patent number: D844001
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 26, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yuan-Ping Chu, Tsai-Yu Lin, Jyh-Chyang Tzou, Chia-Shin Weng, Chia-Chi Lin, Wei-Hao Lan
  • Stylus
    Patent number: D845301
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 9, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yuan-Ping Chu, Tsai-Yu Lin, Jyh-Chyang Tzou, Chia-Shin Weng, Chia-Chi Lin, Wei-Hao Lan