Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: Ultrasound imaging is a non-invasive, non-radioactive, and low cost technology for diagnosis and identification of implantable medical devices in real time. Developing new ultrasound activated coatings is important to broaden the utility of in vivo marking by ultrasound imaging. Ultrasound responsive macro-phase segregated micro-composite thin films were developed to be coated on medical devices composed of multiple materials and with multiple shapes and varying surface area. The macro-phase segregated films having silica micro-shells in polycyanoacrylate produces strong color Doppler signals with the use of a standard clinical ultrasound transducer. Electron microscopy showed a macro-phase separation during slow curing of the cyanoacrylate adhesive, as air-filled silica micro-shells were driven to the surface of the film. The air sealed in the hollow space of the silica shells acted as an ultrasound contrast agent and echo decorrelation of air exposed to ultrasound waves produces color Doppler signals.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: A film deformation element includes a first stack and a second stack. The first stack includes a first passivation layer, a first substrate, a first metal layer and a first dielectric layer. The first substrate is disposed on the first passivation layer. The first metal layer is disposed on the first substrate. The first dielectric layer is disposed on the first metal layer. The second stack is bonded to the first stack, to form a sealing space. The second stack includes a second passivation layer, a second substrate, a second metal layer and a second dielectric layer. The second dielectric layer is disposed on and faces the first dielectric layer. The second metal layer is disposed on the second dielectric layer. The second substrate is disposed on the second metal layer. The second passivation layer is disposed on the second substrate.

Abstract: A flexible hybrid electronic substrate and electronic textile including the same are provided. The flexible hybrid electronic substrate includes a first region and a second region. There is a joint between the first region and the second region. Each of the first region and the second region includes at least one selected from the group consisting of the following structure features: multilayer structure feature, anisotropic structure feature and pre-strained structure feature.

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

Abstract: A multiple sensor-fusing based interactive training system, including a posture sensor, a sensing module, a computing module, and a display module, is provided. The posture sensor is configured to sense posture data and myoelectric data related to a training action. The sensing module is configured to output limb torque data according to the posture data, and output muscle group activation time data according to the myoelectric data. The computing module is configured to respectively convert the limb torque data and the muscle group activation time data into a moment-skeleton coordinate system and a muscle strength eigenvalue-skeleton coordinate system according to a skeleton coordinate system, perform fusion calculation, calculate evaluation data based on a result of the fusion calculation, and judge that the training action corresponds to a known exercise action according to the evaluation data. The display module is configured to display the evaluation data and the known exercise action.

Abstract: The disclosure relates to a dosage forms and combinations of dosage forms useful for effective oral administration of drugs which are otherwise unsuitable for oral administration, owing to acid- and/or protease-mediated degradation. The dosage forms include a self-microemulsifying drug delivery system (SMEDDS) with which the drug is combined and an antacid. When co-administered to a mammal, the dosage form(s) can prevent drug degradation by the strong acid and digestive enzymes normally present in the gastric environment, and can improve water-soluble drug absorption in gastrointestinal (GI) tract. The dosage forms can be used to effectively administer insulin by an oral route, for example, such as in the form of a powder that can be stored for long periods and reconstituted with water or another fluid shortly before administration.

Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

Abstract: The disclosure relates to a dosage forms and combinations of dosage forms useful for effective oral administration of drugs which are otherwise unsuitable for oral administration, owing to acid- and/or protease-mediated degradation. The dosage forms include a self-microemulsifying drug delivery system (SMEDDS) with which the drug is combined and an antacid. When co-administered to a mammal, the dosage form(s) can prevent drug degradation by the strong acid and digestive enzymes normally present in the gastric environment, and can improve water-soluble drug absorption in gastrointestinal (GI) tract. The dosage forms can be used to effectively administer insulin by an oral route, for example, such as in the form of a powder that can be stored for long periods and reconstituted with water or another fluid shortly before administration.

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

Abstract: A patch system includes a patch applied to the body using an adhesive pad. The adhesive pad has a plurality of discrete sections of backing that are independently removed from the adhesive pad during application of the patch to a patient's skin or outerwear.

Abstract: A flexible hybrid electronic (FHE) system includes a carrier, a first redistribution structure on the carrier, a first device on the first redistribution structure, and an encapsulation layer encapsulating the first device. The carrier has a first Young's modulus Y1. The first redistribution structure has a second Young's modulus Y2. The first device and a portion of the encapsulation layer form a top surface of the first redistribution structure to a top surface of the first device is a first portion having a third Young's modulus Y3. The other portion of the encapsulation layer from the top surface of the first device to a top surface of the encapsulation layer is a second portion having a fourth Young's modulus Y4. A ratio of Y3/Y4 is between 1.62 and 1.98; a ratio of Y3/Y2 is between 0.18 and 0.22; and a ratio of Y3/Y1 is between 280.62 and 342.98.

Abstract: An electronic device package structure and a manufacturing method thereof are provided. The electronic device package structure includes a first electronic device layer, a second electronic device layer, and a filling layer disposed between the first electronic device layer and the second electronic device layer, wherein the Young's modulus of the second electronic device layer is less than or equal to the Young's modulus of the first electronic device layer, and the Young's modulus of the filling layer is less than the Young's modulus of the second electronic device layer, and the ratio of the Young's modulus of the first electronic device layer to the Young's modulus of the filling layer is 10 to 1900 and the ratio of the Young's modulus of the second electronic device layer to the Young's modulus of the filling layer is 7.6 to 1300.

Abstract: A chip package structure includes a redistribution circuit layer, at least one chip and an encapsulation material. The redistribution circuit layer includes at least one transistor. The chip is arranged on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The encapsulation material is arranged on the redistribution circuit layer and covers the at least one chip. When the chip package structure includes one or more chips, a position of the chip is taken as a reference for arrangement of a position of the at least one transistor.

Abstract: A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

Abstract: A patch applied to the body to alleviate pain includes a heated section that is powered through a USB cable having temperature and time controls and includes a reusable adhesive for use multiple times.

Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.