Patents by Inventor Tse Nga Ng

Tse Nga Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970572
    Abstract: Embodiments of the presently disclosed technology provide a synergistic combination of a conjugated open-shell donor-acceptor polymer with a carbon-based compound (e.g., reduced graphene oxide) to produce a composite electrode material which demonstrates state-of-the-art capacitance and potential window, with excellent kinetics and cycle life. The conjugated open-shell donor-acceptor polymer may comprise a plurality of alternating electron-rich monomers (i.e., donors) and electron-deficient monomers (i.e., acceptors) bonded together via a conjugated backbone. The conjugated backbone may comprise a connection of n-orbitals of the plurality of monomers in alternating single and double bonds that facilitates unpaired electron delocalization—thereby stabilizing charge for the polymer. The carbon-based compound of the composite electrode material may provide porous, conductive scaffolds for the composite electrode material, resulting in electrodes scalable to microns-thick films with fast kinetics.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: April 30, 2024
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE UNIVERSITY OF SOUTHERN MISSISSIPPI
    Inventors: Tse Nga Ng, Lulu Yao, Jason Azoulay
  • Publication number: 20230087931
    Abstract: Embodiments of the presently disclosed technology provide a synergistic combination of a conjugated open-shell donor-acceptor polymer with a carbon-based compound (e.g., reduced graphene oxide) to produce a composite electrode material which demonstrates state-of-the-art capacitance and potential window, with excellent kinetics and cycle life. The conjugated open-shell donor-acceptor polymer may comprise a plurality of alternating electron-rich monomers (i.e., donors) and electron-deficient monomers (i.e., acceptors) bonded together via a conjugated backbone. The conjugated backbone may comprise a connection of n-orbitals of the plurality of monomers in alternating single and double bonds that facilitates unpaired electron delocalization—thereby stabilizing charge for the polymer. The carbon-based compound of the composite electrode material may provide porous, conductive scaffolds for the composite electrode material, resulting in electrodes scalable to microns-thick films with fast kinetics.
    Type: Application
    Filed: June 14, 2022
    Publication date: March 23, 2023
    Inventors: Tse Nga Ng, Lulu Yao, Jason Azoulay
  • Publication number: 20210401372
    Abstract: A hypertonicity measuring device comprises at least one wearable item. The hypertonicity measuring device comprises at least one communication pathway. The at least one communication pathway is configured to communicate with a processing device. The hypertonicity measuring device comprises a sensor array. The sensor array is disposed to the at least one wearable item. The sensor array comprises a plurality of capacitive pressure sensors. The sensor array is configured to communicate capacitive pressure sensor data to the processing device employing the at least one communication pathway. The plurality of capacitive pressure sensors comprises at least one structured dielectric. The hypertonicity measuring device comprises an inertial measurement unit. The inertial measurement unit is disposed to the at least one wearable item. The inertial measurement unit is configured to communicate motion data to the processing device employing the at least one communication pathway.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Inventors: Harinath Garudadri, Andrew Skalsky, Tse Nga Ng, Michael Yip, Leanne Chukoskie
  • Patent number: 11123013
    Abstract: A hypertonicity measuring device comprises at least one wearable item. The hypertonicity measuring device comprises at least one communication pathway. The at least one communication pathway is configured to communicate with a processing device. The hypertonicity measuring device comprises a sensor array. The sensor array is disposed to the at least one wearable item. The sensor array comprises a plurality of capacitive pressure sensors. The sensor array is configured to communicate capacitive pressure sensor data to the processing device employing the at least one communication pathway. The plurality of capacitive pressure sensors comprises at least one structured dielectric. The hypertonicity measuring device comprises an inertial measurement unit. The inertial measurement unit is disposed to the at least one wearable item. The inertial measurement unit is configured to communicate motion data to the processing device employing the at least one communication pathway.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 21, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Harinath Garudadri, Andrew Skalsky, Tse Nga Ng, Michael Yip, Leanne Chukoskie
  • Patent number: 11122683
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 14, 2021
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Publication number: 20210111359
    Abstract: Embodiments of a shortwave infrared organic photodiode (IR) are disclosed. The IR includes a substrate layer. The IR includes a first electrode layer, the first electrode layer disposed on the substrate layer. The IR includes a first interfacial layer, the first interfacial layer disposed on the first electrode layer. The IR includes a bulk heterojunction, the bulk heterojunction disposed on the first interfacial layer. The bulk heterojunction may include an additive with a dielectric constant above a threshold value. The IR includes a second interfacial layer, the second interfacial layer disposed on the bulk heterojunction. The IR includes a second electrode layer, the second electrode layer disposed on the second interfacial layer.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 15, 2021
    Inventors: Tse Nga Ng, Zhenghui Wu
  • Patent number: 10427397
    Abstract: Disclosed is a conformable, stretchable and electrical conductive structure, which includes an auxetic structure, and a plurality of electrical conductors. The plurality of electrical conductors being incorporated within the auxetic structure, to form conformable, stretchable electrical interconnects, configured based on a design of the auxetic structure and placement of the electrical conductors incorporated with the auxetic structure.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 1, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Corie Lynn Cobb, Steven E. Ready, John S. Paschkewitz
  • Patent number: 10283725
    Abstract: An organic diode has a substrate, a first conductor layer on the substrate, an organic semiconductor layer on the first conductor layer, and a second conductor layer on the organic substrate layer, wherein one of the conductor layers has an injection enhancement.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 7, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Bing R. Hsieh, Tse Nga Ng, Gregory Whiting
  • Publication number: 20190124757
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 25, 2019
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 10245820
    Abstract: A structure can include a first layer of a polymer material and a second layer of the polymer material on the first layer, the first and second layers of the polymer material defining a hollow space that was formed by way of a temporary sacrificial structure that was made of a sublimable material.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 2, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Bing R. Hsieh, Steven E. Ready
  • Patent number: 10229726
    Abstract: A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 12, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David Eric Schwartz, Tse Nga Ng, Ping Mei
  • Patent number: 10178447
    Abstract: A sensor network system that includes a sensor array having a plurality of sensor units that include a plurality of sensor elements, each sensor element configured to generate an electrical signal in response to a chemical environment in the vicinity of the sensor unit. The set of electrical signals generated by the sensor elements of the sensor unit represents a measured signature of the environment in the vicinity of the sensor unit. An analyzer is configured to extract the measured signatures of each sensor unit from sensor unit information signals and to detect a presence and concentration of one or more of the gases of interest based on the measured signatures.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 8, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David E. Schwartz, Tse Nga Ng, Gregory Whiting, Anurag Ganguli, George Daniel
  • Patent number: 10165677
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 25, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 10043605
    Abstract: A sensor including a sensing element comprising conductive features formed on a substrate; wherein the conductive features have been formed from a palladium complex ink composition that has been deposited onto the substrate to form the deposited features and wherein the deposited features have been heated to form the conductive features on the substrate. A method including disposing a palladium complex ink composition onto a substrate to form deposited features; and heating the deposited features to form conductive features on the substrate. A strain gauge sensor including a sensing element comprising conductive features formed on a substrate; wherein the conductive features conform to a two dimensional substrate surface; or wherein the conductive features conform to a three dimensional substrate surface.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: August 7, 2018
    Assignees: Xerox Corporation, Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Sivkheng Kor, Yiliang Wu
  • Patent number: 10020457
    Abstract: A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 10, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, David Eric Schwartz, Janos Veres
  • Publication number: 20180125425
    Abstract: A hypertonicity measuring device comprises at least one wearable item. The hypertonicity measuring device comprises at least one communication pathway. The at least one communication pathway is configured to communicate with a processing device. The hypertonicity measuring device comprises a sensor array. The sensor array is disposed to the at least one wearable item. The sensor array comprises a plurality of capacitive pressure sensors. The sensor array is configured to communicate capacitive pressure sensor data to the processing device employing the at least one communication pathway. The plurality of capacitive pressure sensors comprises at least one structured dielectric. The hypertonicity measuring device comprises an inertial measurement unit. The inertial measurement unit is disposed to the at least one wearable item. The inertial measurement unit is configured to communicate motion data to the processing device employing the at least one communication pathway.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 10, 2018
    Inventors: Harinath Garudadri, Andrew Skalsky, Tse Nga Ng, Michael Yip, Leanne Chukoskie
  • Publication number: 20180114932
    Abstract: An organic diode has a substrate, a first conductor layer on the substrate, an organic semiconductor layer on the first conductor layer, and a second conductor layer on the organic substrate layer, wherein one of the conductor layers has an injection enhancement.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 26, 2018
    Inventors: BING R. HSIEH, Tse Nga Ng, Gregory Whiting
  • Patent number: 9952082
    Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 24, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
  • Patent number: 9874984
    Abstract: Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 23, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Janos Veres
  • Patent number: 9853230
    Abstract: A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 26, 2017
    Assignees: XEROX CORPORATION, PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Yiliang Wu, Biby Esther Abraham