Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: An embodiment is a method and apparatus to sense strain or pressure. A ferroelectric field effect transistor (feFET) structure has a semiconductor layer and a ferroelectric dielectric layer. The feFET structure is capable of sensing strain or pressure. One disclosed feature of the embodiments is a method to fabricate a strain or pressure sensor. A circuit is printed to form a ferroelectric field effect transistor (feFET) structure having a ferroelectric dielectric layer and a semiconductor layer. The feFET structure is capable of sensing strain or pressure.

Abstract: A system of diagnosing a printer or photocopying system using a flexible diagnostic sheet is described. In the system, a thin diagnostic sheet including a plurality of sensors formed on the sheet is run through the paper path of the printing system. The printing system subjects the diagnostic sheet to the printing process, including the deposition of fuser oil and toner on the sheet. Sensors on the sheet record various parameters, including but not limited to the amount of fuser oil deposited and the charge on various toner particles. The information is transmitted to service personnel or the printer end user to enable timely repair of the printer.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

Abstract: Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure; the circuitry substructure can also have channel surface parts that are on semiconductive channel regions, with a set of the channel regions operating as acceptable switches in an application. Or a first substructure's surface can have carrier-active surface parts on electrode regions and line surface parts on line regions; a second substructure can include a transport layer on carrier-active surface parts and, over it, an electrically conductive layer; to prevent leakage, an open region can be defined in the electrically conductive layer over the line surface part and/or an electrically insulating layer portion can cover the line surface part.

Abstract: A layered structure can include laminated first and second substructures and an array with cell regions. The first substructure can include layered active circuitry, the second a top electrode layer. One or both substructure's surface that contacts the other can be on a polymer-containing layer, structured to generate free charge carriers and/or to transport charge carriers. A cell region of the array can include portions of each substructure; the cell region's portion of the first substructure can include a subregion of electrically conductive material and a subregion of semiconductive material, its portion of the second can include part of the top electrode layer. The layered structure can include one or more lamination artifacts on or in the polymer-containing layer; the lamination artifacts can include artifacts of contact pressure, or heat, or of surface shape, and the interface surface can be without vias.

Abstract: A system of diagnosing a printer or photocopying system using a flexible diagnostic sheet is described. In the system, a thin diagnostic sheet including a plurality of sensors formed on the sheet is run through the paper path of the printing system. The printing system subjects the diagnostic sheet to the printing process, including the deposition of fuser oil and toner on the sheet. Sensors on the sheet record various parameters, including but not limited to the amount of fuser oil deposited and the charge on various toner particles. The information is transmitted to service personnel or the printer end user to enable timely repair of the printer.

Abstract: An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.

Abstract: An embodiment is a method and apparatus to construct a shielded cable, wire, or circuit. A first insulator layer is deposited on a first conductor or semiconductor layer. A second conductor or semiconductor layer is deposited on the first insulator layer. A second insulator layer is deposited on the first insulator layer. The second insulator layer covers the second conductor or semiconductor layer and defines a shielded region. A third conductor or semiconductor layer is deposited on the first conductor or semiconductor layer. The third conductor or semiconductor layer covers the first and second insulator layers. At least one of the first, second, and third conductor or semiconductor layers, and the first and second insulator layers is deposited by printing.

Abstract: A method and apparatus for using TFT transistors or MIS capacitors as light-sensing elements in charge mapping arrays. A bias stress may be applied to a plurality of pixels in a charge map array. As a result, charge carriers may be trapped in each of the plurality of pixels responsive to the bias stress, which may be observed as a value shift such as a threshold voltage VT shift. Light may then be transmitted toward the plurality of pixels in the charge map array causing some of the pixels to absorb the light. The trapped charge carriers are released in the pixels that absorbed the light and not released in the pixels that did not absorb the light. The value shift in each of the pixels can be compared to determine which of the pixels absorbed the light.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

Abstract: Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure; the circuitry substructure can also have channel surface parts that are on semiconductive channel regions, with a set of the channel regions operating as acceptable switches in an application. Or a first substructure's surface can have carrier-active surface parts on electrode regions and line surface parts on line regions; a second substructure can include a transport layer on carrier-active surface parts and, over it, an electrically conductive layer; to prevent leakage, an open region can be defined in the electrically conductive layer over the line surface part and/or an electrically insulating layer portion can cover the line surface part.

Abstract: Layered structures such as photosensing arrays include layers in which charge carriers can be transported. For example, a carrier-transporting substructure that includes a solution processing artifact can transport charge carriers that flow to or from it through charge-flow surface parts that are on electrically conductive regions of a circuitry substructure; the circuitry substructure can also have channel surface parts that are on semiconductive channel regions, with a set of the channel regions operating as acceptable switches in an application. Or a first substructure's surface can have carrier-active surface parts on electrode regions and line surface parts on line regions; a second substructure can include a transport layer on carrier-active surface parts and, over it, an electrically conductive layer; to prevent leakage, an open region can be defined in the electrically conductive layer over the line surface part and/or an electrically insulating layer portion can cover the line surface part.

Abstract: In layered structures, channel regions and light-interactive regions can include the same semiconductive polymer material, such as with an organic polymer. A light-interactive region can be in charge-flow contact with a contacting electrode region, and a channel region can, when conductive, provide an electrical connection between the contacting electrode region and other circuitry. For example, free charge carriers can be generated in the light-interactive region, resulting in a capacitively stored signal level; the signal level can be read out to other circuitry by turning on a transistor that includes the channel region. In an array of photosensing cells with organic thin film transistors, an opaque insulating material can be patterned to cover a data line and channel regions of cells along the line, but not extend entirely over the cells' light-interactive regions.

Abstract: A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.