Patents by Inventor Tsuneo Inaba
Tsuneo Inaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098977Abstract: According to one embodiment, a semiconductor device includes a first wiring line provided in a first layer and extending in a first direction, a second wiring line provided in a second layer and extending in the first direction, a first semiconductor layer penetrating the first wiring line without penetrating the second wiring line and extending in a second direction, a second semiconductor layer penetrating the second wiring line without penetrating the first wiring line and extending in the second direction, a first insulating layer provided between the first wiring line and the first semiconductor layer, a second insulating layer provided between the second wiring line and the second semiconductor layer.Type: ApplicationFiled: September 15, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventors: Takashi Inukai, Hiroki Tokuhira, Tsuneo Inaba
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Publication number: 20230200051Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.Type: ApplicationFiled: June 15, 2022Publication date: June 22, 2023Applicant: Kioxia CorporationInventors: Takeshi AOKI, Masaharu WADA, Mamoru ISHIZAKA, Tsuneo INABA
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Patent number: 11665882Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.Type: GrantFiled: September 4, 2020Date of Patent: May 30, 2023Assignee: Kioxia CorporationInventors: Masaharu Wada, Mutsumi Okajima, Tsuneo Inaba, Shinji Miyano
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Publication number: 20230122500Abstract: According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.Type: ApplicationFiled: September 7, 2022Publication date: April 20, 2023Applicant: Kioxia CorporationInventors: Tsuneo INABA, Keisuke NAKATSUKA, Takashi MAEDA
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Publication number: 20220285350Abstract: According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction.Type: ApplicationFiled: May 25, 2022Publication date: September 8, 2022Applicant: Kioxia CorporationInventors: Mutsumi Okajima, Tsuneo Inaba, Hiromitsu Mashita
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Patent number: 11404421Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.Type: GrantFiled: July 13, 2021Date of Patent: August 2, 2022Assignee: KIOXIA CORPORATIONInventor: Tsuneo Inaba
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Patent number: 11201191Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.Type: GrantFiled: September 3, 2019Date of Patent: December 14, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Kawasumi, Tsuneo Inaba
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Publication number: 20210343717Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: Kioxia CorporationInventor: Tsuneo INABA
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Patent number: 11100988Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.Type: GrantFiled: September 9, 2020Date of Patent: August 24, 2021Assignee: KIOXIA CORPORATIONInventors: Tsuneo Inaba, Hiroyuki Takenaka, Akihiko Chiba
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Patent number: 11094698Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.Type: GrantFiled: September 14, 2020Date of Patent: August 17, 2021Assignee: Kioxia CorporationInventor: Tsuneo Inaba
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Publication number: 20210225847Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second, electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.Type: ApplicationFiled: September 4, 2020Publication date: July 22, 2021Applicant: Kioxia CorporationInventors: Masaharu WADA, Mutsumi OKAJIMA, Tsuneo INABA, Shinji MIYANO
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Patent number: 11062770Abstract: According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.Type: GrantFiled: June 24, 2020Date of Patent: July 13, 2021Assignee: KIOXIA CORPORATIONInventors: Tsuneo Inaba, Atsushi Kawasumi
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Publication number: 20210202485Abstract: A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction.Type: ApplicationFiled: September 14, 2020Publication date: July 1, 2021Applicant: Kioxia CorporationInventor: Tsuneo INABA
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Publication number: 20210174870Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.Type: ApplicationFiled: September 9, 2020Publication date: June 10, 2021Applicant: Kioxia CorporationInventors: Tsuneo INABA, Hiroyuki TAKENAKA, Akihiko CHIBA
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Publication number: 20210090645Abstract: According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.Type: ApplicationFiled: June 24, 2020Publication date: March 25, 2021Applicant: Kioxia CorporationInventors: Tsuneo Inaba, Atsushi Kawasumi
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Patent number: 10910032Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.Type: GrantFiled: May 1, 2019Date of Patent: February 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
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Patent number: 10854253Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.Type: GrantFiled: May 1, 2019Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo Inaba
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Publication number: 20200295087Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.Type: ApplicationFiled: September 3, 2019Publication date: September 17, 2020Inventors: Atsushi KAWASUMI, Tsuneo INABA
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Patent number: 10490640Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.Type: GrantFiled: December 6, 2018Date of Patent: November 26, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takeshi Sonehara, Erika Kodama, Nobutaka Nakamura, Tsuneo Inaba, Koichi Nakayama
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Patent number: 10446739Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.Type: GrantFiled: September 12, 2017Date of Patent: October 15, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsuneo Inaba, Tatsuya Kishi, Masahiko Nakayama