Patents by Inventor Tsuneo Inaba

Tsuneo Inaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10854253
    Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo Inaba
  • Publication number: 20200295087
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring above the first wiring and extending in a second direction, first and second memory cells electrically connected in parallel between the first and second wirings and each including a phase change material, a first insulating film on a side portion of the first cell facing the second cell in the second direction, a third wiring above the second wiring and extending in the second direction, a fourth wiring above the third wiring and extending in the first direction, third and fourth memory cells electrically connected between the third and fourth wirings in parallel and each including a phase change material, and a second insulating film on a side of the third cell facing the fourth cell in the second direction. The first film has a higher thermal insulation capacity than the second film.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Inventors: Atsushi KAWASUMI, Tsuneo INABA
  • Publication number: 20200246246
    Abstract: A cosmetic including at least one cyclic silicone represented by formula (1), and having a boiling point of 205 to 255° C. and a viscosity of less than 5 mm2/s (25° C.). This cosmetic has a light touch, a good spread, and excellent water repellency, forms a uniform cosmetic film, can achieve a feeling of use without a strong oily feeling, and has stability over time and cosmetic persistence when a variety of oil such as a silicone, hydrocarbon oil, and ester, an organic ultraviolet absorber, or an oily component being solid at 25° C. is mixed. (Wherein R1 is a monovalent hydrocarbon group having 2 or 3 carbon atoms, R2, R3, R4, R5, and R6 are each independently a monovalent hydrocarbon group having 1 to 3 carbon atoms, “a” is a positive number satisfying 0<a<4, and “b” and “c” are each independently a number of 0 to 3, provided that (a+b+c) <4.
    Type: Application
    Filed: June 22, 2018
    Publication date: August 6, 2020
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Masanao KAMEI, Tomoya KANAI, Takuya ABE, Ryuichi INABA, Tsuneo KIMURA
  • Patent number: 10490640
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Sonehara, Erika Kodama, Nobutaka Nakamura, Tsuneo Inaba, Koichi Nakayama
  • Patent number: 10446739
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuneo Inaba, Tatsuya Kishi, Masahiko Nakayama
  • Patent number: 10446204
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo Inaba
  • Patent number: 10418099
    Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Inuzuka, Tsuneo Inaba, Takayuki Miyazaki, Takeshi Sugimoto
  • Patent number: 10411071
    Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuneo Inaba, Hiroyuki Takenaka
  • Publication number: 20190259436
    Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo INABA
  • Publication number: 20190259438
    Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya KISHI, Tsuneo INABA, Daisuke WATANABE, Masahiko NAKAYAMA, Nobuyuki OGATA, Masaru TOKO, Hisanori AIKAWA, Jyunichi OZEKI, Toshihiko NAGASE, Young Min EEH, Kazuya SAWADA
  • Patent number: 10347690
    Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shingo Nakazawa, Tsuneo Inaba, Hiroyuki Takenaka
  • Patent number: 10325638
    Abstract: According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive effect element including a storage layer and a reference layer; first and second line electrically coupled to the magnetoresistive effect element; and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo Inaba
  • Patent number: 10325640
    Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
  • Publication number: 20190109196
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Takeshi SONEHARA, Erika KODAMA, Nobutaka NAKAMURA, Tsuneo INABA, Koichi NAKAYAMA
  • Publication number: 20190103440
    Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.
    Type: Application
    Filed: August 22, 2018
    Publication date: April 4, 2019
    Inventors: Tsuneo INABA, Hiroyuki TAKENAKA
  • Publication number: 20190088316
    Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.
    Type: Application
    Filed: February 27, 2018
    Publication date: March 21, 2019
    Inventors: Yuki INUZUKA, Tsuneo INABA, Takayuki MIYAZAKI, Takeshi SUGIMOTO
  • Publication number: 20190081101
    Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.
    Type: Application
    Filed: February 26, 2018
    Publication date: March 14, 2019
    Inventors: Shingo NAKAZAWA, Tsuneo INABA, Hiroyuki TAKENAKA
  • Patent number: 10170570
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Sonehara, Erika Kodama, Nobutaka Nakamura, Tsuneo Inaba, Koichi Nakayama
  • Publication number: 20180277743
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuneo INABA, Tatsuya KISHI, Masahiko NAKAYAMA
  • Publication number: 20180277182
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo INABA