Patents by Inventor Tsuneo Inaba
Tsuneo Inaba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446204Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.Type: GrantFiled: September 12, 2017Date of Patent: October 15, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo Inaba
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Patent number: 10418099Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.Type: GrantFiled: February 27, 2018Date of Patent: September 17, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuki Inuzuka, Tsuneo Inaba, Takayuki Miyazaki, Takeshi Sugimoto
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Patent number: 10411071Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.Type: GrantFiled: August 22, 2018Date of Patent: September 10, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsuneo Inaba, Hiroyuki Takenaka
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Publication number: 20190259436Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo INABA
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Publication number: 20190259438Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tatsuya KISHI, Tsuneo INABA, Daisuke WATANABE, Masahiko NAKAYAMA, Nobuyuki OGATA, Masaru TOKO, Hisanori AIKAWA, Jyunichi OZEKI, Toshihiko NAGASE, Young Min EEH, Kazuya SAWADA
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Patent number: 10347690Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.Type: GrantFiled: February 26, 2018Date of Patent: July 9, 2019Assignee: Toshiba Memory CorporationInventors: Shingo Nakazawa, Tsuneo Inaba, Hiroyuki Takenaka
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Patent number: 10325640Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.Type: GrantFiled: March 10, 2017Date of Patent: June 18, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
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Patent number: 10325638Abstract: According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive effect element including a storage layer and a reference layer; first and second line electrically coupled to the magnetoresistive effect element; and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.Type: GrantFiled: March 15, 2017Date of Patent: June 18, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo Inaba
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Publication number: 20190109196Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Inventors: Takeshi SONEHARA, Erika KODAMA, Nobutaka NAKAMURA, Tsuneo INABA, Koichi NAKAYAMA
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Publication number: 20190103440Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.Type: ApplicationFiled: August 22, 2018Publication date: April 4, 2019Inventors: Tsuneo INABA, Hiroyuki TAKENAKA
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Publication number: 20190088316Abstract: A resistance change type memory device includes a first memory cell at a crossing of a first bit line and a first word line, a second memory cell at a crossing of a second bit line and a second word line, a first selection gate line connected to the first bit line, a second selection gate line connected to the second bit line, a dummy gate line adjacent to the first selection gate line, and a control circuit configured to apply a first voltage to the first selection gate line and a second voltage smaller than the first voltage to the dummy gate line when the first selection gate line is selected, and the second voltage or a third voltage smaller than the second voltage to the first selection gate line and the third voltage to the dummy gate line when the second selection gate line is selected.Type: ApplicationFiled: February 27, 2018Publication date: March 21, 2019Inventors: Yuki INUZUKA, Tsuneo INABA, Takayuki MIYAZAKI, Takeshi SUGIMOTO
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Publication number: 20190081101Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.Type: ApplicationFiled: February 26, 2018Publication date: March 14, 2019Inventors: Shingo NAKAZAWA, Tsuneo INABA, Hiroyuki TAKENAKA
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Patent number: 10170570Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.Type: GrantFiled: March 1, 2018Date of Patent: January 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takeshi Sonehara, Erika Kodama, Nobutaka Nakamura, Tsuneo Inaba, Koichi Nakayama
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Publication number: 20180277743Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tsuneo INABA, Tatsuya KISHI, Masahiko NAKAYAMA
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Publication number: 20180277182Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first resistance change memory element and a first transistor, a first word line electrically coupled to a control terminal of the first transistor, and a first circuit configured to, in a reading, apply a first voltage to the first word line during a first period and apply a second voltage higher than the first voltage to the first word line during a second period after the first period.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo INABA
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Patent number: 10020040Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.Type: GrantFiled: March 10, 2017Date of Patent: July 10, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keisuke Nakatsuka, Tsuneo Inaba, Yutaka Shirai
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Publication number: 20180075895Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.Type: ApplicationFiled: March 10, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tatsuya KISHI, Tsuneo INABA, Daisuke WATANABE, Masahiko NAKAYAMA, Nobuyuki OGATA, Masaru TOKO, Hisanori AIKAWA, Jyunichi OZEKI, Toshihiko NAGASE, Young Min EEH, Kazuya SAWADA
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Publication number: 20180075892Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.Type: ApplicationFiled: March 10, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Keisuke NAKATSUKA, Tsuneo INABA, Yutaka SHIRAI
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Publication number: 20180075890Abstract: According to an embodiment, a magnetic storage device includes a memory cell including a magnetoresistive effect element including a storage layer and a reference layer; first and second line electrically coupled to the magnetoresistive effect element; and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.Type: ApplicationFiled: March 15, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Tsuneo INABA
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Patent number: 9865345Abstract: An electronic device includes a semiconductor memory device. The semiconductor memory device includes: a word line driving unit for driving a plurality of word lines; a first circuit area including a first cell array arranged at one side of the word line driving unit; a second circuit area including a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit arranged between the first cell array and the second cell array; a first read control unit; and a second read control unit. The first and second cell arrays include storage cells having variable resistance elements, and the bias voltage generation unit generates a bias voltage based on currents flowing through a first reference resistance element included in the first cell array and a second reference resistance element included in the second cell array.Type: GrantFiled: November 28, 2016Date of Patent: January 9, 2018Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATIONInventors: Dong-Keun Kim, Masahiro Takahashi, Tsuneo Inaba