Abstract: According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each of the memory cells comprises a first transistor, a second transistor and a resistive memory element. One end of the resistive memory element is connected to the first bit line. A drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element. A source region of the first transistor and a source region of the second transistor are connected to the second bit line.

Abstract: According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.

Abstract: A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.

Abstract: A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element, a second transistor having a second gate electrode, third and fourth source/drain electrodes, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element, a first bit line connected to the other terminal of the third resistive memory element, a second bit line connected to the other terminal of each of the first and second resistive memory elements, and first and second word lines connected to each of the first and second gate electrodes.

Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0<R1<R2) are selectively set, wherein resistance gaps ?R1(=R1?R0) and ?R2(=R2?R1) are set to satisfy the relationship of ?R1>?R2.

Abstract: A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portions, and a joining portion formed to join the lower ends thereof. An electric charge storage layer is formed to surround a side surface of the columnar portions. A first conductive layer is formed to surround a side surface of the columnar portions as well as the electric charge storage layer. A plurality of second conductive layers are formed on side surfaces of the joining portion via an insulation film, and function as control electrodes of a plurality of back-gate transistors formed at a respective one of the joining portions.

Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.

Abstract: A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.

Abstract: A memory cell array is formed by arranging memory cells at intersections of plural first wirings and plural second wirings, and a rectifying element and a variable resistive element are connected in series in the memory cell. The variable resistive element has at least a first resistance value and a second resistance value that is higher than the first resistance value. The control circuit selectively drives the first wirings and the second wirings. The control circuit can perform a short-circuit failure countermeasure program operation. In the short-circuit failure countermeasure program operation, the variable resistive element of the memory cell whose rectifying element is in a short-circuit failure state is programmed from the first resistance value to the second resistance value.

Abstract: A semiconductor memory according to an aspect of the invention including first and second bit lines, a word line, a resistive memory element which has one end and the other end, the one end being connected with the first bit line, a selective switch element which has a current path and a control terminal, one end of the current path being connected with the other end of the resistive memory element, the other end of the current path being connected with the second bit line, the control terminal being connected with the word line, a first column switch connected with the first bit line, a second column switch connected with the second bit line, wherein the first and second bit lines is activated and then the word line is activated when starting writing or reading data with respect to the resistive memory element.

Abstract: A magnetic random access memory includes first and second bit lines extending in a first direction, the second bit line being adjacent to the first bit line in a second direction, a first magnetoresistive effect element being connected to the first bit line and having a first fixed layer, a first recording layer, and a first nonmagnetic layer, and a second magnetoresistive effect element being adjacent to the first magnetoresistive effect element in the second direction and being connected to the second bit line and having a second fixed layer, a second recording layer, and a second nonmagnetic layer, the first and second recording layers being formed by a same first layer extending in the second direction.

Abstract: A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1?m?n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

Abstract: A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one.

Abstract: A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

Abstract: A magnetic storage device includes magnetoresistance effect elements. First and second write lines extend along a first direction. Current flows in the first and second write lines only in the first direction and a second direction opposite to the first direction, respectively. A third write line extends along a third direction orthogonal to the first direction. The elements are respectively placed where the first and third write lines cross and the second and third write lines cross. First and second electrodes are provided between the first and third write lines and between the second and third write lines. First and second plugs are respectively connected to the first and second electrodes. The first plug stands at a position apart from the first write line along the third direction. The second plug stands at a position apart from the second write line along the opposite direction to the third direction.

Abstract: A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0<R1<R2) are selectively set, wherein resistance gaps ?R1(=R1?R0) and ?R2(=R2?R1) are set to satisfy the relationship of ?R1>?R2.

Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: A semiconductor memory device includes a write line, at least three first data-writing circuits which are connected to the write line, and memory cells which include a magnetoresistive element, are connected electrically and/or magnetically to the write line, and are arranged between the first data-writing circuits.