Abstract: A magnetron mechanism of an unpowered treadmill contains: a driving body, a one-way transmission element, and a magnetron mechanism. The driving body includes a frame, a connection fence, a front wheel assembly, and a connection shaft. The one-way transmission element is mounted on the connection fence of the frame. The magnetron mechanism is fixed on the connection fence and includes a rotary shaft, a drive wheel, a driven wheel, a belt, a flywheel, a resistance element, and an adjustment unit. The resistance element has a pair of fixing sheets and multiple magnetic parts. Each of the multiple magnetic parts has a rotatable connection portion. The adjustment unit has a steel cable, an end of which is connected with the resistance element so that the steel cable pulls the resistance element to swing along the rotatable connection portion.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.

Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.

Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.

Abstract: A method of fabricating a flexible substrate assembly includes forming a first polyimide layer on a rigid support base, wherein the step of forming the first polyimide layer includes incorporating in a polyamic acid solution, an adhesion promoting agent and a release agent for achieving different adhesion strength at two opposite sides of the first polyimide layer, and forming a flexible second polyimide layer on the first polyimide layer, the second polyimide layer being adhered in contact with the first polyimide layer, and a peeling strength between the first and second polyimide layers being less than a peeling strength between the first polyimide layer and the support base so that the second polyimide layer is peelable from the first polyimide layer while the first polyimide layer remains adhered in contact with the support base.

Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the electronic element and the antenna structure. Therein, the antenna structure has an extension portion and a plurality of support portions connected to the extension portion for supporting the extension portion over the substrate so as to save the surface area of the substrate, thereby meeting the miniaturization requirement of the electronic package.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A method of fabricating a flexible printed circuit includes providing a carrying support comprised of a rigid support base and a release layer adhered in contact with each other, forming a flexible substrate on the carrying support, the formed flexible substrate being adhered in contact with the release layer, applying one or more processing step on the flexible substrate while the flexible substrate is supported by the carrying support, and peeling the flexible substrate with an electric circuit formed thereon from the release layer while the release layer remains adhered in contact with the support base.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: A method of predicting passenger demand includes obtaining a plurality of affecting factors; obtaining a basic passenger demand corresponding to a geographical area at a specific time period; computing at least one first type predicted demands according to the plurality of affecting factors and the basic passenger demand; selecting at least one important affecting factor from the plurality of affecting factors, and computing at least one second type predicted demand according to the at least one important affecting factor; and computing a combined predicted passenger demand according to the first predicted passenger demand and the second predicted passenger demand.

Abstract: A circuit having a tracking loop and a realignment loop is disclosed. The circuit includes: a phase frequency detector (PFD) module for comparing a phase difference of a first input signal and a second input signal; a pump module for converting PFD phase error to charge, wherein the pump module further comprises a low pass filter (LPF); an adjustable realignment module for adjusting a realignment strength, the adjustable realignment module receives a first plurality of inputs from the PFD module, the adjustable realignment module transmits a second plurality of outputs to the pump module; and a ring oscillator unit, the ring oscillator unit receives a first input from the pump module and a second input from the adjustable realignment module, and based on the first and second inputs produces a feedback signal.

Abstract: A method, a server, and a computer-readable recording medium for ride hotspot prediction are provided. The method is applicable to the server and includes the following steps. First, multiple pieces of ride data are obtained, wherein each piece of the ride data includes data respectively associated with candidate factors and a ride spot. Next, data clustering is performed on the ride data according to different regions. At least one positively-related factor which has a positive relation with crowds is selected from the candidate factors by using the ride data for each of the regions to accordingly calculate and generate hotspots in each of the regions.

Abstract: A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.