Abstract: In some embodiments, a digitally controlled oscillator includes a first oscillator a second oscillator and a switch. The second oscillator is selectively enabled in response to a controlled signal. The switch is coupled between the first oscillator and the second oscillator and is selectively conducted in response to the controlled signal, so that an oscillator signal is provided by the first oscillator when the switch is not conducted, and provided by the first oscillator and the second oscillator when the switch is conducted.

Abstract: A time-to-digital converter (TDC) comprises a TDC core and a masking circuit. The TDC core is configured to detect phase difference between a reference signal and a controlled signal. The masking circuit is configured to generate a mask signal based on the reference signal, the controlled signal, and a command signal including information of a predetermined value associated with the reference signal and the controlled signal. The mask signal is used to mask a portion of pulses of the controlled signal from entering the TDC core during detection of phase difference.

Abstract: A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.

Abstract: A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.

Abstract: A control system with a serial interface is provided. The control system includes a programmable database, a first driver, at least one second driver, and a controller. A data is written into the programmable database through a programming method. The first driver is coupled to the programmable database via the serial interface. The at least one second driver is coupled with the first driver. The controller is coupled with the serial interface and accordingly coupled to the programmable database and the first driver via the serial interface. The controller captures the data from the programmable database through the serial interface and adjusts parameters of the first driver and the at least one second driver according to the data.

Abstract: A circuit for a phase detector is provided. A first buffer of the circuit receives a data signal and generates a first modified data signal using the data signal. A notifier receives the data signal and determines whether a violation exists. A first multiplexer receives the first modified data signal and transmits a first multiplexer signal to a second multiplexer. The second multiplexer receives the first multiplexer data signal and the first modified data signal, and transmits a second multiplexer data signal to a flip-flop of the phase detector.

Abstract: A computer device includes a main casing, a computer body disposed in the main casing, a linkage mechanism including first and second sheets and a first shape-memory alloy, and a movable casing pivoted to the main casing. The main casing is for engaging with the movable casing to position the movable casing at an open position exposed from the main casing. A driving end of the first sheet is movably inserted into a slot of the movable casing. The second sheet is disposed on a recess structure of the main casing and pivoted to the first sheet. The first shape-memory alloy is pivoted to one of the second sheet and the recess structure and the driving end for moving the driving end along the slot when being heated to shorten or elongate to push the movable casing from a closed position contained in the recess structure to the open position.

Abstract: An electronic device using method is provided. First, an electronic device and a display device are provided. Then, detecting whether the electronic device is electrically connected to the display device. If the electronic device is electrically connected to the display device, then a tilting angle of the electronic device is sensed. An operating mode of the electronic device corresponding to the display device is determined according to the tilting angle of the electronic device. In addition, an electronic device and an electronic apparatus having the electronic device is also provided.

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract: A circuit for a phase detector is provided. A first buffer of the circuit receives a data signal and generates a first modified data signal using the data signal. A notifier receives the data signal and determines whether a violation exists. A first multiplexer receives the first modified data signal and transmits a first multiplexer signal to a second multiplexer. The second multiplexer receives the first multiplexer data signal and the first modified data signal, and transmits a second multiplexer data signal to a flip-flop of the phase detector.

Abstract: An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.

Abstract: In some embodiments, a PLL comprises an across-stage DCO controller and a DCO. The across-stage DCO controller comprises a first detector and a second tuning code adjustor. The first detector receives a first tuning code in a current stage in which an output frequency of the DCO is tuned by a first step size and generates a first detect signal which indicates whether the first tuning code exceeds a first range that the DCO can be correspondingly tuned in the current stage. The second tuning code adjustor adjusts a second tuning code from a previous stage in which the output frequency of the DCO is tuned by a second step size in response to the first detect signal. The second step size is larger than the first step size. The DCO generates the output frequency in response to codes comprising the adjusted second tuning code.

Abstract: Phase change material microcapsules are obtained using a PMMA prepolymer and an organic-solvent free synthesis process. A polymer monomer and an initiator are subject to pre-polymerization in a water bath to form Polymethyl methacrylate (PMMA) prepolymer which is then prepared to be a stabilizer aqueous solution. A phase change material is added to the stabilizer aqueous solution and liquefied in advance, and stirred to form an emulsion by a homogenizing mixer. A starting agent, a cross-linking agent and a Polymethyl methacrylate methyl ester prepolymer are added to the emulsion containing the phase-change material. The emulsion is further stirred by the homogenizing mixer for micro-emulsification which then aggregates in water bath.

Abstract: A speaker module is provided. The speaker module includes a speaker unit, a box and a shape memory alloy. The box has a rear wall and an opening. The shape memory alloy connects the speaker unit and the rear wall.

Abstract: A belt structure includes a belt, a shape memory alloys, a processing module, and a driving module, wherein the driving module is electrically connected to the processing module. The shape memory alloys is disposed in the belt. The processing module generates a controlling signal according to a triggering signal. The driving module generates a driving signal according to the controlling signal, and supplies the driving signal to the shape memory alloys such that the shape memory alloys is deformed.

Abstract: The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

Abstract: An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure provided on the substrate, wherein the antenna structure has at least a supporting portion and an extending portion supported by the supporting portion over the substrate and surrounding the electronic element; and a shielding structure provided on the substrate and overlapping with the antenna structure, thereby saving the surface area of the substrate so as to meet the miniaturization requirement of the electronic package.

Abstract: A lens module and a speaker module are provided. The lens module includes a lens stand, a base and a shape memory alloy. The shape memory alloy connects the lens stand and the base. The speaker module includes a speaker unit, a box and a shape memory alloy. The box has a rear wall and an opening. The shape memory alloy connects the speaker unit and the rear wall.

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.