Abstract: The disclosure provides a method for manufacturing an electronic package structure, including disposing on a carrier an electronic component and a conductive frame including a plurality of conductive pads and supporting parts; and covering the electronic component and the supporting parts of the conductive frame with an encapsulating layer while allowing the conductive pads to be exposed from the encapsulating layer, thereby increasing the efficiency and reducing the cost of manufacturing processes with the design of the conductive frame. The disclosure further provides the electronic package structure as described above.

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.

Abstract: A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Abstract: A circulation member positioning structure for a ball screw includes a nut and a circulation member. The nut has a threaded channel, a socket, and a positioning notch. The socket is provided on a wall of the threaded channel and the positioning notch is provided on a wall of socket. The circulation member has a circulation portion, a circulation track, and a positioning protrusion. The circulation portion is provided in the socket of the nut. The circulation track is distributed over one lateral of the circulation portion and connects with the threaded channel of the nut. The positioning protrusion is provided on an opposite lateral of the circulation portion for being engaged with the positioning notch of the nut. Thereby, the circulation member positioning structure helps to simplify the assembling work of the circulation member and to remain the nut small despite the insertion of the circulation member.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A vapor chamber structure includes a main body, a fan and perforations. The main body has a heat absorption section, a heat dissipation section and a chamber. The heat absorption section and the heat dissipation section are respectively horizontally disposed on left and right sides of the main body. The heat absorption section is attached to at least one heat source. The chamber is positioned at the heat absorption section and partially extends to the heat dissipation section. The chamber has a capillary structure and at least one perforated section. The perforated section is connected between an upper side and a lower side of the chamber. The fan is disposed on one side of the heat dissipation section. The perforations are formed through the parts of the main body, which parts are free from the chamber and the parts of the main body, where the perforated section is disposed.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A circuit comprises a cascode core circuit and a current adjustor circuit. The cascode core circuit has an output node and a current path (ID). The current adjustor circuit is configured to change a current on the current path in response to a change in a voltage at the output node. The cascode core circuit comprises a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the second transistor is configured as the output node. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current path is through the first terminal of the third transistor.

Abstract: A method of fabricating a flexible substrate assembly includes forming a first polyimide layer on a rigid support base, wherein the step of forming the first polyimide layer includes incorporating in a polyamic acid solution, an adhesion promoting agent and a release agent for achieving different adhesion strength at two opposite sides of the first polyimide layer, and forming a flexible second polyimide layer on the first polyimide layer, the second polyimide layer being adhered in contact with the first polyimide layer, and a peeling strength between the first and second polyimide layers being less than a peeling strength between the first polyimide layer and the support base so that the second polyimide layer is peelable from the first polyimide layer while the first polyimide layer remains adhered in contact with the support base.

Abstract: A method of fabricating a flexible printed circuit includes providing a carrying support comprised of a rigid support base and a release layer adhered in contact with each other, forming a flexible substrate on the carrying support, the formed flexible substrate being adhered in contact with the release layer, applying one or more processing step on the flexible substrate while the flexible substrate is supported by the carrying support, and peeling the flexible substrate with an electric circuit formed thereon from the release layer while the release layer remains adhered in contact with the support base.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A vapor chamber structure includes a main body, a fan and perforations. The main body has a heat absorption section, a heat dissipation section and a chamber. The heat absorption section and the heat dissipation section are respectively horizontally disposed on left and right sides of the main body. The heat absorption section is attached to at least one heat source. The chamber is positioned at the heat absorption section and partially extends to the heat dissipation section. The chamber has a capillary structure and at least one perforated section. The perforated section is connected between an upper side and a lower side of the chamber. The fan is disposed on one side of the heat dissipation section. The perforations are formed through the parts of the main body, which parts are free from the chamber and the parts of the main body, where the perforated section is disposed.

Abstract: A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.

Abstract: A phase lock loop (PLL) such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal.

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

Abstract: A mobile terminal includes: a peripheral interface having four terminals; an I2C interface; a first detection unit adapted to detect if an I2C device is inserted into the peripheral interface; and a first control unit adapted to, when the first detection unit detects there is an I2C device inserted into the peripheral interface, connect the I2C interface with the peripheral interface, such that the I2C interface is connected with the detected I2C device plugged in the peripheral interface. Accordingly, information exchange between mobile terminals and I2C devices can be achieved, thus adaptability of the mobile terminals can be expanded.