Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: The present application related to a method for detecting an object image using a convolutional neural network. Firstly, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the sample image, the detected object image is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the detected object image.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A system and method for recommending emojis to send by a messaging application includes receiving user biosignals from at least one sensor, receiving context information from at least one context source, and selecting, using a rule-based heuristic state selector, a list of plausible user states from possible heuristic states in a heuristic state table based on the received user biosignals and received context information. A state predictor determines, from at least the list of plausible user states and a user model of emojis previously sent in different user states, a list of user states and probabilities that the user will send an emoji for each user state given the context information. The recommended emojis are displayed for selection for sending by the messaging application in order from the highest to the lowest probabilities that the user will send the recommended emojis based on a selected plausible user state.

Abstract: This application provides a method for detecting images of testing object using hyperspectral imaging. Firstly, obtaining a hyperspectral imaging information according to a reference image, hereby, obtaining corresponded hyperspectral image from an input image and obtaining corresponded feature values for operating Principal components analysis to simplify feature values. Then, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the esophageal cancer sample image, the image of the object under detected is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the image of the object under detected.

Abstract: The technical problem of optimizing power consumption of paired user devices is addressed by disabling and resuming short range wireless communication components of the paired user devices. The disabling and resuming of the short range wireless communication components may be determined based on a comparison of a distance between the paired user devices and a threshold distance. The threshold distance may be adjusted by a machine learning model according to user profiles associated with the paired user devices. The distance between the paired user devices may be determined based on location data of the paired user devices. The location data may be obtained by global positioning systems (GPS) mounted on the paired user devices. The location data may be communicated between the paired user devices via a messaging server.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.

Abstract: A cell array includes a substrate and a conductive line. The substrate has active areas in the substrate. The conductive line is disposed across the active areas and includes work function nodes and line sections which are horizontally and alternately arranged with work function nodes, in which each work function node is between two of the active areas.

Abstract: A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.

Abstract: A thermoplastic artificial leather is provided, which includes a first structure layer, a second structure layer, a plurality of recycled particles, and a third structure layer, in which the second structure layer is disposed on the first structure layer, the plurality of recycled particles disposed on the second structure layer, and the third structure layer is disposed to cover the plurality of recycled particles. According to above stacked structure, the thermoplastic artificial leather with environment friendly is formed, and the plurality of recycled particles is processed in a physical manner, which can solve the problem, the environmental protection issue, caused by the use of solvent to process the recycled particle in the prior art. Use of the material characteristics of each structure layer to reprocess the recycled particles, so the reprocess procedure without using any solvent, so the environmental pollution and the production cost are greatly reduced.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.