Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10011822
    Abstract: A phytase having improved thermostability is disclosed. The phytase has a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is one of mutations A to D. The mutation A is to substitute amino acids at positions 143 and 262 with cysteine, the mutation B is to substitute amino acids at positions 259 and 312 with cysteine, the mutation C is to substitute amino acids at positions 205 and 257 with cysteine, and the mutation D is to substitute amino acids at positions 264 and 309 with cysteine.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 3, 2018
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO., LTD.
    Inventors: Tzu-Hui Wu, Ya-Shan Cheng, Hui-Lin Lai, Cheng-Yen Lin, Tsung-Yu Ko, Jian-Wen Huang, Chun-Chi Chen, Rey-Ting Guo
  • Publication number: 20180174914
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 21, 2018
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen, Hsin-Lung Chao, Chen Chu-Hsuan
  • Publication number: 20180174916
    Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 21, 2018
    Inventors: Wei-Shuo HO, Tsung-Yu CHIANG, Chia-Ming CHANG, Jyun-Ming LIN
  • Publication number: 20180166451
    Abstract: In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.
    Type: Application
    Filed: January 31, 2017
    Publication date: June 14, 2018
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180166548
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 14, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching HUANG, Tsung-Yu CHIANG
  • Publication number: 20180166329
    Abstract: A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate electrode; forming a source/drain (S/D) feature that is adjacent to the gate stack; forming a dielectric layer over the gate stack and the S/D feature; forming a contact hole in the dielectric layer to expose the S/D feature, wherein the contact hole includes a first sidewall that is formed by the spacer layer and part of the dielectric layer; doping an upper portion of the first sidewall; and performing an etching process thereby cleaning oxides in the contact hole.
    Type: Application
    Filed: April 12, 2017
    Publication date: June 14, 2018
    Inventors: Cheng-Chien HUANG, Tsung-Yu CHIANG
  • Patent number: 9997527
    Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180151754
    Abstract: A memory device and an operation method thereof are provided. The memory device includes a semiconductor substrate and an oxide-nitride-oxide (ONO) gate structure located on the semiconductor substrate. The ONO gate structure includes a bottom oxide layer, a top oxide layer and a nitride layer. The nitride layer is located between the bottom oxide layer and the top oxide layer. The bottom oxide layer is located closer to the semiconductor substrate than the top oxide layer. The bottom oxide layer has a first thickness, and the top oxide layer has a second thickness smaller the first thickness. The operation method includes an erasing operation and a programming operation. Electrons are attracted into the ONO gate structure through the bottom oxide layer in the programming operation. Electrons trapped in the ONO gate structure escape from the ONO gate structure through the top oxide layer.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 31, 2018
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180151753
    Abstract: A semiconductor device includes a substrate, a trap storage structure, a control gate, a cap structure, a word line well, a source line, spacers, a gap oxide layer, a word line and a gate oxide layer. The trap storage structure includes a first oxide layer, a nitride layer and a second oxide layer stacked on the substrate. The control gate is directly on the trap storage structure. The cap structure is stacked on the control gate to form a stacked structure. The word line well and the source line are disposed in the substrate at opposite sides of the stacked structure. The spacers are on sidewalls of the stacked structure. The gap oxide layer is on a sidewall of one spacer. The word line is on the word line well and the gap oxide layer. The gate oxide layer is between the word line and the word line well.
    Type: Application
    Filed: December 14, 2016
    Publication date: May 31, 2018
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180151472
    Abstract: A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between the die and the lid, wherein the lid includes a protrusion protruded towards the surface of the die and the thermally conductive material surrounds the protrusion. Also, a method of manufacturing a semiconductor structure includes providing a die including a surface, providing a lid, removing a portion of the lid to form a protrusion, disposing a thermally conductive material between the surface of the die and the lid, wherein the protrusion of the lid is surrounded by the thermally conductive material. Further, an apparatus for manufacturing a semiconductor structure and a method of manufacturing a semiconductor structure by the apparatus are disclosed.
    Type: Application
    Filed: February 16, 2017
    Publication date: May 31, 2018
    Inventors: TSUNG-YU CHEN, WENSEN HUNG, HUNG-CHI LI, CHENG-CHIEH HSIEH, TUNG-LIANG SHAO, CHIH-HANG TUNG
  • Publication number: 20180151585
    Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.
    Type: Application
    Filed: January 3, 2017
    Publication date: May 31, 2018
    Inventors: Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180151586
    Abstract: A storage device includes a semiconductor substrate, a control gate, a word line, a dielectric layer, a charge storage nitride layer, and a blocking layer. The semiconductor substrate has a source region and a drain region. The control gate and a word line are disposed over the semiconductor substrate and located between the source and drain regions. The dielectric layer is in contact with the semiconductor substrate and disposed between the semiconductor substrate, the control gate, and the word line. The charge storage nitride layer is disposed between the dielectric layer and the control gate. The blocking layer is disposed between the charge storage nitride layer and the control gate.
    Type: Application
    Filed: February 9, 2017
    Publication date: May 31, 2018
    Inventors: Yung-Chun Tu, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 9977554
    Abstract: A touch display panel includes a substrate, a first electrode layer, and a second electrode layer. The first and second electrode layers are disposed on the substrate. The second electrode layer electrically connects to the first electrode layer and includes a plurality of sensing electrodes. Each sensing electrode includes a plurality of first conductive lines and a plurality of second conductive lines connected to each other. The first and second conductive lines are respectively arranged along first and second directions, wherein the second direction is different from the first direction. In one of two adjacent sensing electrodes, the outermost first conductive line has at least one first edge and at least one second edge connected to the first edge. The first edge corresponds to one of the second conductive lines of the other one of the two adjacent sensing electrodes, and has a curved shape.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 22, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Yu Wang, Pei-Chieh Chen, Chao-Hsiang Wang
  • Publication number: 20180134338
    Abstract: A disc brake caliper of a bicycle includes a main body, a first bolt, an intermediate member, a second bolt, and a tubing connector. The main body has an oil passage and a first tapped hole communicating with the oil passage. The first bolt is screwed into the first tapped hole, with a first exposed section exposed out of the main body. The intermediate member fits around the first exposed section through a first perforation, and has a second tapped hole, which extends in a direction different from that of the first perforation. The intermediate member can be rotated relative to the first exposed section. The second bolt is screwed in the second tapped hole, with a second exposed section exposed out of the intermediate member. The tubing connector fits around the second exposed section through a second perforation, and can be rotated relative to the second exposed section.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Applicant: LEE CHI ENTERPRISES COMPANY LTD.
    Inventor: TSUNG-YU HSIEH
  • Publication number: 20180138317
    Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Jing-Ru Lin, Cheng-Bo Shu, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180138129
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Tsung-Yu CHIANG, Chen KUANG-HSIN, Bor-Zen TIEN, Tzong-Sheng CHANG
  • Publication number: 20180122818
    Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180115688
    Abstract: A camera module including a lens holder, a lens barrel, a first lens set, a second lens set, an image sensing component and a driver is provided. The lens barrel is disposed on the lens holder. The first lens set is disposed in the lens barrel. The second lens set is fixed in the lens holder. The first lens set and the second lens set include at least one lens respectively. The image sensing component is disposed in the lens holder. The driver is configured to drive the lens barrel to enable the first lens set to move along a direction parallel to an axis direction of the optical axis. The driver adjusts a position of the first lens set so as to form a gap between the first lens set and the second lens set and along the optical axis.
    Type: Application
    Filed: May 17, 2017
    Publication date: April 26, 2018
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventor: Tsung-Yu Lin
  • Publication number: 20180115689
    Abstract: An assembly method of a camera module is provided. The camera module includes a first and second lens set respectively including at least one lens. The assembly steps include: providing a substrate, a lens holder, and an image sensing device, wherein the image sensing device is located in a space formed by the substrate and the lens holder, and the lens holder includes a limiting portion; disposing the second lens set in the space; assembling a barrel in the limiting portion, wherein the first lens set is disposed in the barrel, the second lens set is located between the first lens set and the image sensing device, and the first and second lens sets and the image sensing device have a common optical axis; inspecting the imaging of the image sensing device; and adjusting a position of the barrel in the limiting portion according to the inspection result.
    Type: Application
    Filed: October 26, 2017
    Publication date: April 26, 2018
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Tsung-Yu Lin, Shih-Chieh Yen, Ti-Lun Liu, Ming-Huang Shih
  • Patent number: 9947766
    Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Chiang, Kuang-Hsin Chen