Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.

Abstract: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.

Abstract: A dye-sensitized photoelectric conversion apparatus having enhanced energy conversion efficiency and a production method thereof are provided. The dye-sensitized photoelectric conversion apparatus which has semiconductor layer (13) containing a photosensitizing dye (14) and is constituted such that a charge carrier generated by allowing light to incident in the photosensitizing dye (14) is drawn out through the semiconductor layer (13), in which the semiconductor layer (13) is constituted by a plurality of regions (13A to 13D) having different energy levels from one another of a passage through which the charge carrier is transferred. Further, the plurality of regions (13A to 13D) are arranged such that the energy levels are reduced stepwise and/or continuously in the direction of drawing the charge carrier out.

Abstract: A transistor-type protection device includes: a semiconductor substrate; a well of a first-conductivity-type formed in the semiconductor substrate; a source region of a second-conductivity-type formed in the well; a gate electrode formed on the well via a gate insulating film at one side of the source region; plural drain regions of a second-conductivity-type formed apart from each other and respectively separated at a predetermined distance from a well part immediately below the gate electrode film; and a resistive connection part connecting between the plural drain regions with a predetermined electric resistance.

Abstract: A transistor-type protection device includes: a semiconductor substrate; a well including a first-conductivity-type semiconductor formed in the semiconductor substrate; a source region including a second-conductivity-type semiconductor formed in the well; a gate electrode formed above the well via a gate insulating film at one side of the source region; a drain region including the second-conductivity-type semiconductor formed within the well apart at one side of the gate electrode; and a resistive breakdown region including a second-conductivity-type semiconductor region in contact with the drain region at a predetermined distance apart from the well part immediately below the gate electrode, wherein a metallurgical junction form and a impurity concentration profile of the resistive breakdown region are determined so that a region not depleted at application of a drain bias when junction breakdown occurs in the drain region or the resistive breakdown region may remain in the resistive breakdown region.

Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

Abstract: A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first conductivity type well region, a second conductivity type channel layer formed on the surface of the well region, a first wire that connects an end of the second conductivity type channel layer to the first conductivity type drain, a second wire that connects the other end of the second conductivity type channel layer to a power source, and a third wire 208 that connects the first conductivity type well region to the gate of the first field effect transistor. This semiconductor device and manufacturing method thereof enables low power consumption and simple control of threshold voltage values as well as decreases the number of conventional manufacturing processes.

Abstract: A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

Abstract: A gas detector capable of accurately measuring particular components (odors or the like) contained in an ambient gas to be measured, being compact, and capable of being easily formed to be portable, or producing low noise and capable of being small-sized. Having zero gas cylinder (9) as a supplying unit of a zero gas and component parts disposed within its enclosure (2) and using syringe (3) as a gas intake/exhaust unit, it alternately introduces a test gas, i.e., an ambient gas taken in from outside enclosure (2) through piping (12a), and the zero gas supplied from zero gas cylinder (9) into sensor unit (7) and measures the test gas, while having operation of each unit controlled by data processor (11). Thus, accurate measurement of the test gas is achieved by relatively comparing results of measurement on the gases at each measurement. In addition, gas detector (1) can be moved to a spot where measurement is to be made to have the test gas there measured.

Abstract: A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first conductivity type well region, a second conductivity type channel layer formed on the surface of the well region, a first wire that connects an end of the second conductivity type channel layer to the first conductivity type drain, a second wire that connects the other end of the second conductivity type channel layer to a power source, and a third wire 208 that connects the first conductivity type well region to the gate of the first field effect transistor. This semiconductor device and manufacturing method thereof enables low power consumption and simple control of threshold voltage values as well as decreases the number of conventional manufacturing processes.

Abstract: A dye-sensitized photoelectric conversion apparatus having enhanced energy conversion efficiency and a production method thereof are provided. The dye-sensitized photoelectric conversion apparatus which has semiconductor layer (13) containing a photosensitizing dye (14) and is constituted such that a charge carrier generated by allowing light to incident in the photosensitizing dye (14) is drawn out through the semiconductor layer (13), in which the semiconductor layer (13) is constituted by a plurality of regions (13A to 13D) having different energy levels from one another of a passage through which the charge carrier is transferred. Further, the plurality of regions (13A to 13D) are arranged such that the energy levels are reduced stepwise and/or continuously in the direction of drawing the charge carrier out.

Abstract: A gas detector capable of accurately measuring particular components (odors or the like) contained in an ambient gas to be measured, being compact, and capable of being easily formed to be portable, or producing low noise and capable of being small-sized. Having zero gas cylinder (9) as a supplying unit of a zero gas and component parts disposed within its enclosure (2) and using syringe (3) as a gas intake/exhaust unit, it alternately introduces a test gas, i.e., an ambient gas taken in from outside enclosure (2) through piping (12a), and the zero gas supplied from zero gas cylinder (9) into sensor unit (7) and measures the test gas, while having operation of each unit controlled by data processor (11). Thus, accurate measurement of the test gas is achieved by relatively comparing results of measurement on the gases at each measurement. In addition, gas detector (1) can be moved to a spot where measurement is to be made to have the test gas there measured.

Abstract: A photoelectric transducer having a relatively simple structure and capable of reducing the loss of light energy of incident light and conductor loss due to electrical resistance. A photoelectric transducer 16A includes a conductive layer 2; a electrolytic layer 3 that is in contact with the conductive layer 2; a charge separating layer 4; a transparent conductive layer 5 and a metal lines 7, which are in contact with the charge separating layer 4; and convex lenses 8 converging incident light 15 on openings 20 provided between the metal lines 7, the incident light 15 being converged on the charge separating layer 4 by the convex lenses 8. Electrons generated by photoelectric conversion move to the exterior through an external circuit 17 having a low resistivity.

Abstract: Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first conductivity type well region, a second conductivity type channel layer formed on the surface of the well region, a first wire that connects an end of the second conductivity type channel layer to the first conductivity type drain, a second wire that connects the other end of the second conductivity type channel layer to a power source, and a third wire 208 that connects the first conductivity type well region to the gate of the first field effect transistor. This semiconductor device and manufacturing method thereof enables low power consumption and simple control of threshold voltage values as well as decreases the number of conventional manufacturing processes.

Abstract: Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A semiconductor device having a semiconductor resistance element is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration which is difficult to control, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a donor concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A semiconductor device which has complementary logic gates, including: a field effect transistor 101 having a first conductivity type channel, a first conductivity type well region 202 formed on a semiconductor substrate 102, a second conductivity type channel layer 203 formed on the surface of the region 202, a first wire 112 that connects an end 204 of the second conductivity type channel layer 203 to a first conductivity type drain region 106, a second wire 208 that connects the other end 205 of the second conductivity type channel layer 203, and a third wire 208 that connects the first conductivity type well region 202 to a second power source that has the same polarity as a first power source; and manufacturing method thereof. This semiconductor device and manufacturing method enables low power consumption and simple control of threshold voltage values as well as avoiding increases in the number of manufacturing processes.

Abstract: Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: A semiconductor device including field effect transistors having different threshold voltages formed on a common base, characterized by including: a first field effect transistor having a p-n junction gate; and a second field effect transistor having a Schottky junction gate; wherein a threshold voltage of the first field effect transistor is set on the basis of a depth of the p-n junction, and a threshold voltage of the second field effect transistor is set on the basis of selection of a barrier potential of the Schottky junction.