Abstract: A pinch-off voltage measurement circuit for measuring the pinch-off voltage of a field effect transistor. The circuit uses a measuring capacitor and connection circuit. A voltage is applied to the transistor and an impedance change is detected via the connection circuit.

Abstract: A manufacturing method of a junction field effect transistor, promising a low ON resistance, high maximum drain current and linearity with a high transmission gain and also enabling the gate length to be reduced, makes a channel layer by sequentially epitaxially growing an undoped GaAs layer, n.sup.+ -type GaAs layer and n-type GaAs layer on a semi-insulating GaAs substrate via a GaAs buffer layer. Through an opening formed in a diffusion mask in form of a SiN.sub.x film on the n-type GaAs layer, Zn is diffused into the n-type GaAs layer to form a p.sup.+ -type gate region. From above the diffusion mask, a gate metal layer is deposited, and patterned to make a gate electrode in the opening of the diffusion mask in self-alignment with the p.sup.+ -type gate region.

Abstract: Disclosed is a method of fabricating a semiconductor device in which a plurality of FETs (Field Effect Transistors) having different threshold values are formed on the same substrate. The method includes the steps of: implanting ions of an impurity having a first conducting type in active regions of the plurality of FETs, to simultaneously form channel layers in the active regions; and implanting ions of an impurity having a second conducting type at bottom portion of the channel layers, to simultaneously form buried layers at the bottom portions of the channel layers; wherein a carrier concentration distribution in the active region of a specific one of the plurality of FETs is changed depending on a desired threshold value of the specific FET. In the semiconductor device fabricated in accordance with the method, each of the FETs is allowed to exhibit a desired electric characteristic and a desired controllability of a threshold value.