Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: An image synchronization method for multiple cameras, comprising the following steps: receiving a first video of a first camera and a second video of a second camera; capturing a first object in the first video and a second object in the second video; determining whether the first object is the same as the second object; if yes, transferring a first coordinate of the first object and a second coordinate of the second object to a uniform coordinate; regulating a timing sequence of the second video to calculate a plurality of multi-object tracking accuracy values for the second video and the first video and identifying a maximum multi-object tracking accuracy value; generating a time compensation value according to a time different corresponding to the maximum multi-object tracking accuracy value and synchronizing the first camera and the second camera according to the time compensation.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: The embodiments of the disclosure provide a method for dynamically controlling shooting parameters of a camera and a tracking device. The method includes: determining a plurality of time frames, wherein the time frames include a plurality of first time frames and a plurality of second time frames; controlling the camera of the tracking device to shoot a first image with a first exposure parameter in each of the first time frames and accordingly performing an environment detection; controlling the camera of the tracking device to shoot a second image with a second exposure parameter in each of the second time frames and accordingly performing a first specific detection, wherein the second exposure parameter is lower than the first exposure parameter.

Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.

Abstract: Disclosed herein is a method for identifying and treating an early-stage hepatocellular carcinoma (HCC) in a subject. The method mainly includes determining the level of serum amyloid A (SAA) protein, and providing anti-cancer treatment based on the determined level of SAA protein. According to some embodiments of the present disclosure, the anti-cancer treatment is provided when the determined level of SAA protein is lower than that of a first control sample, or when the determined level of SAA protein is higher than that of a second control sample. In some embodiments, the first control sample is derived from a subject having a late stage HCC, and the second control sample is derived from a subject having a liver disease that is any of hepatitis, liver cirrhosis, or a combination thereof.

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).

Abstract: A micro LED and a manufacturing method thereof are provided. The micro LED includes a first semiconductor layer, an active layer, and a second semiconductor layer that are successively stacked together. The first semiconductor layer and the second semiconductor layer are of different types. The active layer includes a first quantum well layer and a second quantum well layer stacked together. The second quantum well layer and the second semiconductor layer form a nanoring. The first quantum well layer is configured to emit light of a first color. The second quantum well layer forming a sidewall of the nanoring is configured to emit light of a second color different from the first color. The first semiconductor layer is electrically coupled to a first electrode, and the second semiconductor layer is electrically coupled to a second electrode. A manufacturing method for a micro LED is provided.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A wire-to-board connector includes an insulating body, a number of first conductive terminals, a number of second conductive terminals, a number of first cables and a number of second cables. The first conductive terminals are arranged at intervals along a first direction. The first conductive terminal includes a first elastic mating portion and a first cable connection portion. The second conductive terminal includes a second elastic mating portion and a second cable connection portion. The first cable connection portion and the second cable connection portion are arranged in a misalignment manner along a second direction perpendicular to the first direction. The first elastic mating portion and the second elastic mating portion protrude beyond a first surface of the insulating body so as to abut against metal conductive pads of a circuit board. Besides, a wire-to-board connector assembly having the wire-to-board connector is also disclosed.

Abstract: A joint test action group transmission system includes a host terminal and a slave terminal. The slave terminal includes a test access port (TAP) circuit, an internal memory, and a memory interface controller. The TAP circuit includes a test data register set. The memory interface controller stores the data received from the TAP circuit to the internal memory. The host terminal transmits a set of download instruction bits to the TAP circuit to have the TAP circuit select the test data register set, and have the TAP circuit enter a data shift status to receive a data package through the test data register set. During the process of receiving the data package, the TAP circuit remains in the data shift status to receive the address and at least one piece of data stored in the data package continuously.

Abstract: Systems and methods for application identification in accordance with embodiments of the invention are disclosed. In one embodiment, a user device includes a processor and memory configured to store an application, a session manager, an application identifier, and at least one shared library, and the processor is configured by the session manager to communicate the application identifier and the application identifier data to an authentication server and permit the execution of the application in response to authentication of the application by the authentication server.

Abstract: An electronic device includes a substrate, an organic layer, a first insulating layer, and a first spacer. The organic layer is disposed on the substrate and includes a first opening and a second opening. The first insulating layer includes a first portion in the first opening and a second portion connected to the first portion and on the organic layer. The first spacer is disposed on the substrate and overlaps the second portion. In a top view of the electronic device, the second portion between the first opening and the second opening has a first length, the first spacer has a second length, the organic layer between the first opening and the second opening has a third length. The first length is greater than or equal to the second length and less than or equal to the third length.

Abstract: A cable connector includes an insulating body, a number of cable conductive terminals, a number of cables and a grounding shell. The insulating body extends along a first direction and a second direction. The cable conductive terminals include a number of first cable conductive terminals disposed in a first row and a number of second cable conductive terminals disposed in a second row. Each of the first cable conductive terminals includes a first mating portion and a first mounting portion. Each of the second cable conductive terminals includes a second mating portion and a second mounting portion. The first mounting portions are flush with the second mounting portions. The grounding shell includes a spacer between the first cable conductive terminals and the second cable conductive terminals to improve signal integrity. A connector assembly having the cable connector is also disclosed.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: An electrical connector includes a built-in circuit board, an insulating member and a shielding shell. The built-in circuit board includes an extension portion. The insulating member is fixed to the built-in circuit board. The insulating member includes an attachment portion. The shielding shell is provided with a mating space. The electrical connector includes a tongue plate extending into the mating space. The tongue plate includes at least the extension portion and the attachment portion. A thickness of the tongue plate includes at least a thickness of the extension portion and a thickness of the attachment portion. By adjusting the thickness of the attachment portion, the tongue plate with a target thickness can be obtained, thereby reducing the requirement on the built-in circuit board. A method of making the electrical connector is also disclosed.

Abstract: The disclosure provides a manufacturing method of an electronic device, including the following steps. A substrate is provided. A conductive layer is formed on the substrate. An insulating layer is formed on the conductive layer. The insulating layer is patterned to form a first opening and a second opening. A first electronic element is disposed in the first opening and the first electronic element is electrically connected to the conductive layer. A second electronic element is disposed in the second opening and the second electronic element is electrically connected to the conductive layer. The first electronic element and the second electronic element have different functions.

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a secure area and a non-secure area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a secure mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

Abstract: Disclosed are surface-treated copper foils having at least one treated surface that exhibit high conductivity and a set of surface properties. Also provided are flexible copper-clad laminates and printed circuits made therefrom. The present printed circuits exhibit low insertion loss and are suitable for use in high speed/high frequency applications.