Patents by Inventor Tung-Tsun Chen

Tung-Tsun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11360073
    Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
  • Patent number: 11320395
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Patent number: 11293897
    Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei Lee, Pei-Wen Liu
  • Publication number: 20220065812
    Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG
  • Publication number: 20210399187
    Abstract: A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures.
    Type: Application
    Filed: March 16, 2021
    Publication date: December 23, 2021
    Inventors: Yu-Jie HUANG, Chung-Hui CHEN, Jui-Cheng HUANG, Tung-Tsun CHEN
  • Publication number: 20210389273
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Application
    Filed: June 14, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Publication number: 20210376091
    Abstract: A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.
    Type: Application
    Filed: February 12, 2021
    Publication date: December 2, 2021
    Inventors: Chung-Hui CHEN, Tung-Tsun CHEN, Jui-Cheng HUANG
  • Publication number: 20210325339
    Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.
    Type: Application
    Filed: May 10, 2021
    Publication date: October 21, 2021
    Inventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
  • Patent number: 11137370
    Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
  • Patent number: 11119101
    Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 14, 2021
    Inventors: Jui-Cheng Huang, Chin-Hua Wen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Ching-Hui Lin
  • Publication number: 20210263022
    Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng HUANG, Chin-Hua WEN, Tung-Tsun CHEN, Cheng-Hsiang HSIEH, Yu-Jie HUANG, Ching-Hui LIN
  • Patent number: 11002704
    Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
  • Publication number: 20210116413
    Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng HUANG, Yi-Hsien CHANG, Chin-Hua WEN, Chun-Ren CHENG, Shih-Fen HUANG, Tung-Tsun CHEN, Yu-Jie HUANG, Ching-Hui LIN, Sean CHENG, Hector CHANG
  • Publication number: 20210109059
    Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.
    Type: Application
    Filed: November 30, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor manufacturing Co., Ltd.
    Inventors: Tung-Tsun CHEN, Jui-Cheng Huang, Kun-Lung Chen, Cheng-Hsiang Hsieh
  • Patent number: 10876997
    Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 29, 2020
    Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
  • Patent number: 10866209
    Abstract: A microfluidic system includes a semiconductor substrate having a first surface and an opposite, parallel second surface, a first bioFET sensor and a second bioFET sensor. An isolation layer is disposed on the second surface of the semiconductor substrate and has a first opening over the first bioFET sensor and a second opening over the second bioFET sensor. An interface layer is disposed in at least each of the first opening and the second opening. The system includes a readout circuit having a differential amplifier designed to measure a difference between signals associated with the first bioFET sensor and the second bioFET sensor. The system also includes a microfluidic network designed to deliver fluid to the interface layer disposed in each of the first opening and the second opening.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 15, 2020
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Tung-Tsun Chen, Yu-Jie Huang, Penny Hsiao
  • Patent number: 10852271
    Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 1, 2020
    Inventors: Tung-Tsun Chen, Jui-Cheng Huang, Kun-Lung Chen, Cheng-Hsiang Hsieh
  • Patent number: 10845450
    Abstract: A device includes a first biosensor of a biosensor array; a second biosensor of a biosensor array; a readout circuit electrically connected to the biosensor array; a decoder electrically connected to the biosensor array; a voltage generator electrically connected to the biosensor array; and a decision system electrically connected to the voltage generator and the readout circuit.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 24, 2020
    Inventors: Chin-Hua Wen, Jui-Cheng Huang, Yi-Shao Liu, Chun-Wen Cheng, Tung-Tsun Chen
  • Publication number: 20200348282
    Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.
    Type: Application
    Filed: July 8, 2020
    Publication date: November 5, 2020
    Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
  • Publication number: 20200333320
    Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.
    Type: Application
    Filed: June 11, 2020
    Publication date: October 22, 2020
    Inventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang