Patents by Inventor Tung-Tsun Chen
Tung-Tsun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11491455Abstract: An integrated circuit includes an interconnection structure, first and second sensing pixels over the interconnection structure, and an isolation layer over the first and second sensing pixels. Each of the first and second sensing pixels includes a bio-sensing device, a temperature-sensing device, one or more heating elements adjacent to the bio-sensing device and the temperature-sensing device, and a sensing film over the bio-sensing device. The isolation layer includes a first opening configured to expose the sensing film of the first sensing pixel without exposing the sensing film of the second sensing pixel and a second opening configured to expose the sensing film of the second sensing pixel without exposing the sensing film of the first sensing pixel.Type: GrantFiled: November 15, 2019Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
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Publication number: 20220352451Abstract: A method of manufacturing an integrated circuit structure includes forming active regions, forming source/drain regions, and forming conductive segments resulting in a thermoelectric structure including a p-type region positioned on a front side of the substrate, an n-type region positioned on the front side of the substrate, and a wire on the front side of the substrate configured to electrically couple the p-type region to the n-type region. The method includes forming a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, forming a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate, and electrically coupling an energy device to each of the first and second power structures.Type: ApplicationFiled: July 5, 2022Publication date: November 3, 2022Inventors: Yu-Jie HUANG, Chung-Hui CHEN, Jui-Cheng HUANG, Tung-Tsun CHEN
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Publication number: 20220333251Abstract: The present disclosure provides a gas sensor. The gas sensor includes a substrate, a conductor layer over the substrate, wherein the conductor layer includes a conductive pattern including a plurality of openings, the openings being arranged in a repeating pattern, an insulating layer in the plurality of openings and over a top surface of the conductive pattern, wherein the conductive pattern is embedded in the insulating layer, and a gas sensing film over a portion of the insulating layer.Type: ApplicationFiled: June 20, 2022Publication date: October 20, 2022Inventors: MING-TA LEI, CHIA-HUA CHU, HSIN-CHIH CHIANG, TUNG-TSUN CHEN, CHUN-WEN CHENG
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Patent number: 11446630Abstract: An integrated circuit includes a plurality of sensing pixels, each sensing pixel including a sensing film portion, a bio-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a first switching device coupled between the bio-sensing device and a first signal path, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and a second switching device coupled between the temperature-sensing device and a second signal path.Type: GrantFiled: November 15, 2019Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
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Patent number: 11414763Abstract: The present disclosure provides a method of manufacturing a gas sensor. The method includes the following operations: a substrate is received; a conductor layer is formed over the substrate; the conductor layer is patterned to form a conductor with a plurality of openings by an etching operation, the openings being arranged in a repeating pattern, a minimal dimension of the opening being about 4 micrometers; and a gas-sensing film is formed over the conductor.Type: GrantFiled: December 6, 2019Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Ta Lei, Chia-Hua Chu, Hsin-Chih Chiang, Tung-Tsun Chen, Chun-Wen Cheng
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Publication number: 20220221421Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Katherine H. Chiang, Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei Lee, Pei-Wen Liu
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Patent number: 11360073Abstract: A semiconductor device includes a circuit layer and a nanopore layer. The nanopore layer is formed on the circuit layer and is formed with a pore therethrough. The circuit layer includes a circuit unit configured to drive a biomolecule through the pore and to detect a current associated with a resistance of the nanopore layer, whereby a characteristic of the biomolecule can be determined using the currents detected by the circuit unit.Type: GrantFiled: June 11, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kun-Lung Chen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Jui-Cheng Huang
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Patent number: 11320395Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.Type: GrantFiled: June 14, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
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Patent number: 11293897Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.Type: GrantFiled: May 16, 2019Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Katherine H. Chiang, Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei Lee, Pei-Wen Liu
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Publication number: 20220065812Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG
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Publication number: 20210399187Abstract: A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures.Type: ApplicationFiled: March 16, 2021Publication date: December 23, 2021Inventors: Yu-Jie HUANG, Chung-Hui CHEN, Jui-Cheng HUANG, Tung-Tsun CHEN
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Publication number: 20210389273Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.Type: ApplicationFiled: June 14, 2020Publication date: December 16, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
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Publication number: 20210376091Abstract: A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.Type: ApplicationFiled: February 12, 2021Publication date: December 2, 2021Inventors: Chung-Hui CHEN, Tung-Tsun CHEN, Jui-Cheng HUANG
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Publication number: 20210325339Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.Type: ApplicationFiled: May 10, 2021Publication date: October 21, 2021Inventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
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Patent number: 11137370Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.Type: GrantFiled: July 29, 2019Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
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Patent number: 11119101Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.Type: GrantFiled: January 13, 2017Date of Patent: September 14, 2021Inventors: Jui-Cheng Huang, Chin-Hua Wen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Ching-Hui Lin
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Publication number: 20210263022Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Cheng HUANG, Chin-Hua WEN, Tung-Tsun CHEN, Cheng-Hsiang HSIEH, Yu-Jie HUANG, Ching-Hui LIN
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Patent number: 11002704Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.Type: GrantFiled: August 31, 2016Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
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Publication number: 20210116413Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Cheng HUANG, Yi-Hsien CHANG, Chin-Hua WEN, Chun-Ren CHENG, Shih-Fen HUANG, Tung-Tsun CHEN, Yu-Jie HUANG, Ching-Hui LIN, Sean CHENG, Hector CHANG
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Publication number: 20210109059Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.Type: ApplicationFiled: November 30, 2020Publication date: April 15, 2021Applicant: Taiwan Semiconductor manufacturing Co., Ltd.Inventors: Tung-Tsun CHEN, Jui-Cheng Huang, Kun-Lung Chen, Cheng-Hsiang Hsieh