Abstract: Gate-all-around (GAA) devices and methods for fabricating such are disclosed herein. An exemplary GAA device includes a first semiconductor layer disposed over a substrate. A gate structure is disposed over and wraps a portion of the first semiconductor layer, such that the gate structure separates a source region of the first semiconductor layer and a drain region of the first semiconductor layer. A channel region of the first semiconductor layer is defined between the source region and the drain region. A dielectric layer is disposed adjacent to the first semiconductor layer, where the dielectric layer extends along an entirety of the source region of the first semiconductor layer and an entirety of the drain region of the first semiconductor layer. A second semiconductor layer disposed over the source region of the first semiconductor layer, the drain region of the first semiconductor layer, and the dielectric layer.

Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.

Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: Disclosed herein are human trophoblast stem (hTS) cells, differentiated cells thereof, derivatives thereof such as cellular mass, and uses thereof. The isolation of hTS cells can express FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. The hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In the hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. The hTS cells could apply to human cell differentiation and for gene and cell-based therapies.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.

Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.

Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.

Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

Abstract: Existence of human trophoblast stem (hTS) cells has been suspected but unproved. The isolation of hTS cells is reported in the early stage of chorionic villi by expressions of FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. These facts suggest that differentiation of the hTS cells play an important role in implantation and placentation. hTS cells could apply to human cell differentiation and for gene and cell-based therapies.

Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.