Patents by Inventor Tung-Ying Lee

Tung-Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of manufacturing the same
    Patent number: 11189522
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee, Chih Chieh Yeh
  • Semiconductor device and manufacturing method thereof
    Patent number: 11183584
    Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Tung Ying Lee, Wei-Sheng Yun, Jin Cai
  • INTERCONNECT STRUCTURE AND METHOD
    Publication number: 20210343588
    Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 4, 2021
    Inventors: Bo-Jiun Lin, Yu Chao Lin, Tung Ying Lee
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20210335676
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • PHASE-CHANGE MEMORY DEVICE AND METHOD
    Publication number: 20210336138
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Application
    Filed: August 13, 2020
    Publication date: October 28, 2021
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Semiconductor device structure with semiconductor wire
    Patent number: 11158542
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
  • SEMICONDUCTOR DEVICE, MEMORY CELL AND METHOD OF FORMING THE SAME
    Publication number: 20210328139
    Abstract: A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • MEMORY CELL, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME
    Publication number: 20210328141
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210320185
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying LEE, Tse-An CHEN, Tzu-Chung WANG, Miin-Jang CHEN, Yu-Tung YIN, Meng-Chien YANG
  • Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same
    Publication number: 20210313455
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    Publication number: 20210305100
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
  • Separate Epitaxy Layers for Nanowire Stack GAA Device
    Publication number: 20210305390
    Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
  • Phase-Change Memory Device and Method
    Publication number: 20210305508
    Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.
    Type: Application
    Filed: October 16, 2020
    Publication date: September 30, 2021
    Inventors: Tung Ying Lee, Shao-Ming Yu, Yu Chao Lin
  • METHOD AND RELATED APPARATUS FOR INTEGRATING ELECTRONIC MEMORY IN AN INTEGRATED CHIP
    Publication number: 20210296461
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Method of manufacturing a semiconductor device with separated merged source/drain structure
    Patent number: 11127740
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Meng-Hsuan Hsiao, Tsung-Lin Lee, Chih Chieh Yeh, Yee-Chia Yeo
  • HUMAN TROPHOBLAST STEM CELLS AND USES THEREOF
    Publication number: 20210278395
    Abstract: Disclosed herein are human trophoblast stem (hTS) cells, differentiated cells thereof, derivatives thereof such as cellular mass, and uses thereof. The isolation of hTS cells can express FGF4, FGFR-2, Oct4, Thy-1, and stage-specific embryonic antigens distributed in different compartments of the cell. The hTS cells are able to derive into specific cell phenotypes of the three primitive embryonic layers, produce chimeric reactions in mice, and retain a normal karyotype and telomere length. In the hTS cells, Oct4 and fgfr-2 expressions can be knockdown by bFGF. The hTS cells could apply to human cell differentiation and for gene and cell-based therapies.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 9, 2021
    Inventors: Jau-Nan LEE, Tony Tung-Ying LEE, Yuta LEE
  • Gate all around device, method for manufacturing FinFET device, and method for manufacturing gate all around device
    Patent number: 11114303
    Abstract: In a method, a semiconductor substrate is etched to form a trench, such that the trench defines a channel portion. A hard mask layer is deposited over sidewalls of the channel portion. The semiconductor substrate is anisotropically etched to deepen the trench, such that the deepened trench further defines a base portion under the channel portion and the hard mask layer. The hard mask layer is removed from the sidewalls of the channel portion. The deepened trench is filled with an isolation material. The isolation material is recessed to form an isolation structure, in which the channel portion protrudes from the isolation structure.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung-Ying Lee
  • A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    Publication number: 20210272952
    Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Tung Ying LEE, Ziwei FANG, Yee-Chia YEO, Meng-Hsuan HSIAO
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210226042
    Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Meng-Hsuan HSIAO, Tung Ying LEE, Wei-Sheng YUN, Jin CAI
  • Point-of-sale base with object recognition camera module thereon
    Patent number: D931363
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 21, 2021
    Assignee: FLYTECH TECHNOLOGY CO., LTD
    Inventors: Yi-Heng Tseng, Tung-Ying Lee, Tzu-Wei Huang, Che-Wei Lin