Abstract: Photonic circuits are disclosed having an efficient optical power distribution network. Laser chips (InP) having different wavelengths are flip-chip assembled near the center of a silicon photonic chip. Each InP die has multiple optical lanes, but a given die has only one wavelength. Waveguides formed in the photonic chip are optically connected to the lanes, and fan out to form multiple waveguide sets, where each waveguide set has one of the waveguides from each of the different wavelengths, i.e., one waveguide from each InP die. The waveguide network is optimized to minimize the number of crossings that any given waveguide may have, and no waveguide having a particular wavelength crosses another waveguide of the same wavelength. The unique arrangements of light sources and waveguides allows the use of a smaller number of more intense laser sources, particularly in applications such as performance-optimized datacenters where liquid cooling systems may be leveraged.

Abstract: Embodiments of the invention are directed a waveguide having a first waveguide segment that includes a set of first waveguide segment confinement parameters; a second waveguide segment having routing bends and a set of second waveguide segment confinement parameters; and a third waveguide segment having a set of third waveguide segment confinement parameters. The waveguide is configured to guide optical data according to an asymmetric optical-loss performance curve that is a plot of the sets of first, second, and third waveguide segment confinement parameters on a first axis; and a level of optical-loss performance that results from the sets of first, second, and third waveguide segment confinement parameters on a second axis. The sets of first, second, and third waveguide segment confinement parameters are configured to, collectively, maximize a predetermined worst-case optical-loss performance level of the asymmetric optical-loss performance curve within a range of waveguide fabrication tolerances.

Abstract: Embodiments of the invention are directed a waveguide having a first waveguide segment that includes a set of first waveguide segment confinement parameters; a second waveguide segment having routing bends and a set of second waveguide segment confinement parameters; and a third waveguide segment having a set of third waveguide segment confinement parameters. The waveguide is configured to guide optical data according to an asymmetric optical-loss performance curve that is a plot of the sets of first, second, and third waveguide segment confinement parameters on a first axis; and a level of optical-loss performance that results from the sets of first, second, and third waveguide segment confinement parameters on a second axis. The sets of first, second, and third waveguide segment confinement parameters are configured to, collectively, maximize a predetermined worst-case optical-loss performance level of the asymmetric optical-loss performance curve within a range of waveguide fabrication tolerances.

Abstract: Systems and methods for coupling optical fiber to a photonic chip are described. The apparatus may include a low index contrast waveguide overlapping a region of a photonic chip, a high index contrast waveguide at least partially embedded within the overlapped region of the photonic chip, where the high index contrast waveguide comprises a tapered region and a fixed-width routing region, and where the tapered region comprises an adiabatic crossing region and a wide waveguide region connecting the adiabatic crossing region and the fixed-width routing region. A rate of increase of the width of the high index contrast waveguide with respect to position along the length of the high index contrast waveguide is substantially non-linear within the adiabatic crossing region and substantially asymmetric about a minimum slope point.

Abstract: A method for assembling a waveguide connector includes positioning a polymer waveguide in one or more insertion structures within an inner portion of a cap where the polymer waveguide has alignment features. The method also includes inserting a ferrule into the inner portion of the cap such that an inner wall of the cap seals around the assembled connector and heating the polymer waveguide and the ferrule to a first temperature with the ferrule comprising alignment features and having a different coefficient of thermal expansion from the polymer waveguide. The alignment features of the polymer waveguide align with the alignment features of the ferrule when the polymer waveguide and the ferrule are heated to the first temperature.

Abstract: Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof.

Abstract: A method for assembling a waveguide connector includes positioning a polymer waveguide in one or more insertion structures within an inner portion of a cap where the polymer waveguide has alignment features. The method also includes inserting a ferrule into the inner portion of the cap such that an inner wall of the cap seals around the assembled connector and heating the polymer waveguide and the ferrule to a first temperature with the ferrule comprising alignment features and having a different coefficient of thermal expansion from the polymer waveguide. The alignment features of the polymer waveguide align with the alignment features of the ferrule when the polymer waveguide and the ferrule are heated to the first temperature.

Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

Abstract: A method of forming a laser including device is provided that in one embodiment includes providing a laser chip including at least one ridge structure that provides an alignment features. The method further includes bonding a type IV photonics chip to the laser chip, wherein a vertical alignment feature from the type IV photonics chip is inserted in a recess relative to the at least one ridge structure that provides the alignment features of the laser structure.

Abstract: Methods of forming waveguide connectors include positioning a polymer waveguide in one or more insertion structures within an inner portion of a cap where the polymer waveguide has alignment features on a connection end face corresponding to one or more components of an assembled connector. The method can include inserting a ferrule into the inner portion of the cap such that an inner wall of the cap seals around the assembled connector to prevent contaminants from entering the inner portion and heating the polymer waveguide and the ferrule to a first temperature with the ferrule comprising alignment features and having a different coefficient of thermal expansion from the polymer waveguide. The alignment features of the polymer waveguide align with the alignment features of the ferrule when the polymer waveguide and the ferrule are heated to the first temperature.

Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Abstract: A method of forming a laser including device is provided that in one embodiment includes providing a laser chip including at least one ridge structure that provides an alignment features. The method further includes bonding a type IV photonics chip to the laser chip, wherein a vertical alignment feature from the type IV photonics chip is inserted in a recess relative to the at least one ridge structure that provides the alignment features of the laser structure.

Abstract: Techniques are provided for single edge coupling of chips with integrated waveguides. For example, a package structure includes a first chip with a first critical edge, and a second chip with a second critical edge. The first and second chips include integrated waveguides with end portions that terminate on the first and second critical edges. The second chip includes a signal reflection structure that is configured to reflect an optical signal propagating in one or more of the integrated waveguides of the second chip. The first and second chips are edge-coupled at the first and second critical edges such that the end portions of the integrated waveguides of the first and second chips are aligned to each other, and wherein all signal input/output between the first and second chips occurs at the single edge-coupled interface.

Abstract: Various embodiments are directed to a connector for coupling optical signals to a semiconductor device. In one embodiment, the connector includes a connector member having a recessed portion to arrange a plurality of waveguides formed side-by-side in a transverse direction. A backup member is arranged within the recessed portion interposing the plurality of waveguides between the connector member and the backup member. The recessed portion includes a plurality of ridges arranged in a staggered pattern relative to the plurality of waveguides for positioning the plurality of waveguides relative to the connector.

Abstract: A method for assembling a semiconductor device includes: receiving a first chip including a plurality of first bonding pads, a first standoff and a second standoff, wherein a first solder is deposited on each of the first bonding pads; depositing a second solder on each of the first and second standoffs; arranging a second chip over the first chip, wherein the second chip includes a plurality of second bonding pads, and at least one of the second bonding pads has a corresponding first bonding pad; heating the second chip over a melting point of the second solder to melt the second solder, and placing the second chip on the first chip to touch and solidify the second solder on each of the first and second standoffs; performing a reflow process to melt the first solder on each of the first bonding pads so that at least one of the first solders touches a corresponding second bonding pad; and waiting a predetermined period of time to allow the second chip to move until a side edge of the second chip touches a wav

Abstract: Systems and methods for nanofiller in an optical interface are provided. One system includes a fiber-optic interface for one or more optical fibers that includes a body including one or more grooves defined therein. At least one groove in the one or more grooves is configured to receive a corresponding optical fiber of the one or more optical fibers. The at least one groove of the one or more grooves is further configured to receive an adhesive to attach the body to a portion of the corresponding optical fiber. Further, fiber-optic interface includes a suspended structure associated with the at least one groove configured to couple light between the suspended structure and the corresponding optical fiber. Also, the adhesive comprises nanofiller configured to support an alignment of the suspended structure with the corresponding optical fiber within the at least one groove.