Patents by Inventor Tze-Chiang Chen
Tze-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050106836Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.Type: ApplicationFiled: January 10, 2005Publication date: May 19, 2005Inventors: Tze-Chiang Chen, Liang-Kai Han
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Publication number: 20050093100Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.Type: ApplicationFiled: November 3, 2003Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-chiang Chen, Guy Cohen, Alexander Reznicek, Devendra Sadana, Ghavam Shahidi
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Patent number: 6887783Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.Type: GrantFiled: August 28, 2003Date of Patent: May 3, 2005Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
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Patent number: 6885080Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.Type: GrantFiled: February 22, 2002Date of Patent: April 26, 2005Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Liang-Kai Han
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Patent number: 6878611Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.Type: GrantFiled: January 2, 2003Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: Devendra K. Sadana, Stephen W. Bedell, Tze-Chiang Chen, Kwang Su Choe, Keith E. Fogel
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Publication number: 20040251232Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.Type: ApplicationFiled: February 25, 2004Publication date: December 16, 2004Applicant: International Business Machines CorporationInventors: Tze-chiang Chen, Stuart S. P. Parkin
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Patent number: 6812114Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form a first implant region of the first ions in the Si-containing substrate. Following the implantation of first ions, a first annealing step is performed which forms a buried semi-insulating or insulating region within the Si-containing substrate. Next, second ions that are insoluble in the semi-insulating or insulating region are selectively implanted into portions of the buried semi-insulating or insulating region. After the selective implant step, a second annealing step is performed which recrystallizes the buried semi-insulating or insulating region that includes second ions to the same crystal structure as the original Si-containing substrate.Type: GrantFiled: April 10, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Devendra K. Sadana
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Publication number: 20040173907Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.Type: ApplicationFiled: March 23, 2004Publication date: September 9, 2004Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
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Publication number: 20040132267Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.Type: ApplicationFiled: January 2, 2003Publication date: July 8, 2004Applicant: International Business Machines CorporationInventors: Devendra K. Sadana, Stephen W. Bedell, Tze-Chiang Chen, Kwang Su Choe, Keith E Fogel
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Publication number: 20040115873Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.Type: ApplicationFiled: August 28, 2003Publication date: June 17, 2004Inventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftall E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
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Patent number: 6657261Abstract: A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.Type: GrantFiled: January 9, 2001Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Fariborz Assaderaghi, Tze-chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 6635517Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.Type: GrantFiled: August 7, 2001Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim, Ghavam G. Shahidi
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Publication number: 20030194847Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form a first implant region of the first ions in the Si-containing substrate. Following the implantation of first ions, a first annealing step is performed which forms a buried semi-insulating or insulating region within the Si-containing substrate. Next, second ions that are insoluble in the semi-insulating or insulating region are selectively implanted into portions of the buried semi-insulating or insulating region. After the selective implant step, a second annealing step is performed which recrystallizes the buried semi-insulating or insulating region that includes second ions to the same crystal structure as the original Si-containing substrate.Type: ApplicationFiled: April 10, 2002Publication date: October 16, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Devendra K. Sadana
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Publication number: 20030162400Abstract: A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.Type: ApplicationFiled: February 22, 2002Publication date: August 28, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Liang-Kai Han
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Publication number: 20030134499Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.Type: ApplicationFiled: January 15, 2002Publication date: July 17, 2003Applicant: International Business Machines CorporationInventors: Tze-Chiang Chen, Brett H. Engel, John A. Fitzsimmons, Terence Kane, Naftali E. Lustig, Ann McDonald, Vincent McGahay, Soon-Cheon Seo, Anthony K. Stamper, Yun Yu Wang, Erdem Kaltalioglu
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Patent number: 6593205Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of the first ions in the Si-containing substrate. Following the first implant step, a selective implant process is employed wherein second ions that are insoluble in SiO2 are incorporated into portions of the Si-containing substrate. The second ions employed in the selective implant step are capable of preventing the implant region of first ions from forming an oxide region during a subsequent annealing step. An annealing step is then performed which causes formation of a buried oxide region in the implant region of first ions that does not include the second ions.Type: GrantFiled: February 21, 2002Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Tze-chiang Chen, Devendra K. Sadana
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Patent number: 6566177Abstract: A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench.Type: GrantFiled: October 25, 1999Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: Carl J. Radens, Gary B. Bronner, Tze-chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy, Devendra K. Sadana, Ghavam Ghavami Shahidi, Scott R. Stiffler
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Patent number: 6521949Abstract: Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.Type: GrantFiled: May 3, 2001Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Ghavam G. Shahidi
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Publication number: 20030032251Abstract: A method of forming a self-aligned gettering region within an SOI substrate is provided. Specifically, the inventive method includes the steps of forming a disposable spacer on each vertical sidewall of a patterned gate stack region, the patterned gate stack region being formed on a top Si-containing layer of an SOI substrate; implanting gettering species into the top Si-containing layer not protected by the disposable spacer and patterned gate stack region; and removing the disposable spacer and annealing the implanted gettering species so as to convert said species into a gettering region.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta, Paul A. Ronsheim, Ghavam G. Shahidi
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Publication number: 20020164841Abstract: Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.Type: ApplicationFiled: May 3, 2001Publication date: November 7, 2002Applicant: International Business Machines CorporationInventors: Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Ghavam G. Shahidi