Patents by Inventor Tze-Liang Lee

Tze-Liang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device, FinFET device and methods of forming the same
    Patent number: 11271083
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
  • Method of making semiconductor device having first and second epitaxial materials
    Patent number: 11257951
    Abstract: A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly Su, Chii-Horng Li, Ming-Hua Yu, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee
  • Apparatus for manufacturing a thin film and a method therefor
    Patent number: 11244822
    Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Fu Hsiao, Kuang-Yuan Hsu, Pei-Ren Jeng, Tze-Liang Lee
  • Seamless gap fill
    Patent number: 11239310
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • PHOTORESIST LAYER OUTGASSING PREVENTION
    Publication number: 20220028684
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.
    Type: Application
    Filed: January 22, 2021
    Publication date: January 27, 2022
    Inventors: Yen-Yu CHEN, Chib-Cheng LIU, Yi-Ohen KUO, Jr-Hung Li, Tze-Liang LEE, Ming-Hui WENG, Yahru CHENG
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND PATTERN FORMATION METHOD
    Publication number: 20220005687
    Abstract: In a pattern formation method, a photoresist layer is formed over a substrate by combining a first precursor and a second precursor in a vapor state to form a photoresist material. The first precursor is an organometallic having a formula MaRbXc, where M is one or more selected from the group consisting of Sn, Bi, Sb, In, and Te, R is an alkyl group that is substituted by different EDG and/or EWG, X is a halide or sulfonate group, and 1?a?2, b?1, c?1, and b+c?4. The second precursor is water, an amine, a borane, and/or a phosphine. The photoresist material is deposited over the substrate, and selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: May 10, 2021
    Publication date: January 6, 2022
    Inventors: Chih-Cheng LIU, Ming-Hui WENG, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Semiconductor Device and Method
    Publication number: 20210407794
    Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
  • METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE
    Publication number: 20210391465
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: Eric PENG, Chao-Cheng CHEN, Chii-Horng LI, Ming-Hua YU, Shih-Hao LO, Syun-Ming JANG, Tze-Liang LEE, Ying-Hao HSIEH
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20210375779
    Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20210343529
    Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
  • Field-effect transistor and method of manufacturing the same
    Patent number: 11164948
    Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Jung Ho, Jr-Hung Li, Tze-Liang Lee, Pei-Yu Chou, Chi-Ta Lee
  • Method for forming semiconductor device that includes covering metal gate with multilayer dielectric
    Patent number: 11164789
    Abstract: A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Jung Ho, Yu-Shih Wang, Tze-Liang Lee
  • FORMING ISOLATION REGIONS FOR SEPARATING FINS AND GATE STACKS
    Publication number: 20210335670
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.
    Type: Application
    Filed: July 20, 2020
    Publication date: October 28, 2021
    Inventors: Chung-Ting Ko, Tai-Chun Huang, Jr-Hung Li, Tze-Liang Lee, Chi On Chui
  • METHOD FOR FORMING SEMICONDUCTOR DEVICE THAT INCLUDES COVERING METAL GATE WITH MULTILAYER DIELECTRIC
    Publication number: 20210327760
    Abstract: A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Jung HO, Yu-Shih WANG, Tze-Liang LEE
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210302839
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210302833
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: October 15, 2020
    Publication date: September 30, 2021
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERN
    Publication number: 20210305040
    Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Yi-Chen KUO, Chih-Cheng LIU, Ming-Hui WENG, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20210305047
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Inventors: Jia-Lin WEI, Ming-Hui WENG, Chih-Cheng LIU, Yi-Chen KUO, Yen-Yu CHEN, Yahru CHENG, Jr-Hung LI, Ching-Yu CHANG, Tze-Liang LEE, Chi-Ming YANG
  • Dielectric spacer to prevent contacting shorting
    Patent number: 11107902
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu
  • Source/drain recess in a semiconductor device
    Patent number: 11107921
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh