Patents by Inventor Tze-Liang Lee

Tze-Liang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patterning methods for semiconductor devices
    Patent number: 10867839
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu, Tze-Liang Lee
  • Patterning method for semiconductor devices and structures resulting therefrom
    Patent number: 10867794
    Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Szu-Ping Tung, Chun-Kai Chen, Jen Hung Wang, Tze-Liang Lee
  • Semiconductor device and method
    Patent number: 10867807
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • FinFET with rounded source/drain profile
    Patent number: 10861975
    Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng, Tze-Liang Lee
  • Doping profile for strained source/drain region
    Patent number: 10861971
    Abstract: The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Semiconductor device having first and second epitaxial materials
    Patent number: 10854748
    Abstract: A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly SU, Pang-Yen Tsai, Tze-Liang Lee, Chii-Horng Li, Yen-Ru Lee, Ming-Hua Yu
  • Method to reduce etch variation using ion implantation
    Patent number: 10854729
    Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Ziwei Fang, Chii-Horng Li, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang
  • Interconnect structure and method
    Patent number: 10840134
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-yi Ruan
  • MOS Devices Having Epitaxy Regions with Reduced Facets
    Publication number: 20200357921
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Method for Manufacturing a Semiconductor Device
    Publication number: 20200357634
    Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Wan-Lin Tsai, Jung-Hau Shiu, Ching-Yu Chang, Jen Hung Wang, Shing-Chyang Pan, Tze-Liang Lee
  • Stress Modulation for Dielectric Layers
    Publication number: 20200350433
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • Source and Drain Stressors with Recessed Top Surfaces
    Publication number: 20200343381
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Semiconductor device having fins
    Patent number: 10811537
    Abstract: A device includes a semiconductor substrate, an isolation structure, and an epitaxial fin portion. The semiconductor substrate has an implanted region. The implanted region has a bottom fin portion thereon, in which a depth of the implanted region is smaller than a thickness of the semiconductor substrate. The isolation structure surrounds the bottom fin portion. The epitaxial fin portion is disposed over a top surface of the bottom fin portion, in which the implanted region of the semiconductor substrate includes oxygen and has an oxygen concentration lower than about 1·E+19 atoms/cm3.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Yu Lin, Ming-Hua Yu, Tze-Liang Lee, Chan-Lon Yang
  • MOS devices with non-uniform p-type impurity profile
    Patent number: 10797173
    Abstract: An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Treatment system and method
    Patent number: 10796898
    Abstract: A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Kuang-Yuan Hsu, Tze-Liang Lee
  • Patterning Method for Semiconductor Devices and Structures Resulting Therefrom
    Publication number: 20200312662
    Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Szu-Ping Tung, Chun-Kai Chen, Jen Hung Wang, Tze-Liang Lee
  • Source/drain recess in a semiconductor device
    Patent number: 10784375
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • SEAMLESS GAP FILL
    Publication number: 20200295131
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Yen-Chun HUANG, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • MOS devices having epitaxy regions with reduced facets
    Patent number: 10734520
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Method for manufacturing a semiconductor device
    Patent number: 10727045
    Abstract: A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Lin Tsai, Jung-Hau Shiu, Ching-Yu Chang, Jen Hung Wang, Shing-Chyang Pan, Tze-Liang Lee