Patents by Inventor Tzu-Chiang Chen

Tzu-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200043802
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Application
    Filed: May 31, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Hung-Li CHIANG, Tzu-Chiang CHEN
  • Publication number: 20200044061
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Application
    Filed: September 27, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching CHENG, Hung-Li CHIANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Publication number: 20200044060
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Application
    Filed: April 26, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching CHENG, Hung-Li CHIANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Publication number: 20200043803
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Publication number: 20200006155
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
    Type: Application
    Filed: February 21, 2019
    Publication date: January 2, 2020
    Inventors: Hung-Li CHIANG, Chih-Liang CHEN, Tzu-Chiang CHEN, I-Sheng CHEN, Lei-Chun CHOU
  • Publication number: 20200006154
    Abstract: A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.
    Type: Application
    Filed: February 21, 2019
    Publication date: January 2, 2020
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN
  • Patent number: 10522622
    Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Publication number: 20190393102
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 26, 2019
    Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
  • Publication number: 20190393357
    Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 26, 2019
    Inventors: I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H. Diaz
  • Patent number: 10504796
    Abstract: A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
  • Publication number: 20190355724
    Abstract: Present disclosure provides a hybrid semiconductor transistor structure, including a substrate, a first transistor on the substrate, a channel of the first transistor including a fin and having a first channel height, a second transistor adjacent to the first transistor, a channel of the second transistor including a nanowire, and a separation laterally spacing the fin from the nanowire. The first channel height is greater than the separation. Present disclosure also provides a method for manufacturing the hybrid semiconductor transistor structure.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Inventors: HUNG-LI CHIANG, I-SHENG CHEN, TZU-CHIANG CHEN
  • Publication number: 20190348498
    Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 14, 2019
    Inventors: CHAO-CHING CHENG, I-SHENG CHEN, TZU-CHIANG CHEN, SHIH-SYUAN HUANG, HUNG-LI CHIANG
  • Publication number: 20190341469
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Chao-Ching CHENG, Yu-Lin YANG, Wei-Sheng YUN, Chen-Feng HSU, Tzu-Chiang CHEN
  • Publication number: 20190279911
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10403550
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang, I-Sheng Chen, Szu-Wei Huang
  • Publication number: 20190267292
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung-Ying Lee, Szu-Wei Huang, Huan-Sheng Wei
  • Publication number: 20190259877
    Abstract: A method for forming a semiconductor structure includes receiving a substrate including a dielectric structure; forming a first recess in the substrate; forming a dielectric spacer over a sidewall of the first recess; forming a first semiconductor layer to fill the first recess; removing the dielectric structure to form a second recess over the substrate; and forming a second semiconductor layer to fill the second recess. The dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: CHAO-CHING CHENG, CHEN-FENG HSU, YU-LIN YANG, JUNG-PIAO CHIU, TZU-CHIANG CHEN
  • Publication number: 20190252266
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Publication number: 20190237573
    Abstract: A method for forming a multi-gate semiconductor device includes providing a substrate including at least a fin structure and a dummy gate structure over the fin structure and the substrate, disposing a conductive spacer over sidewalls of the dummy gate structure, portions of the fin structure are exposed from the dummy gate structure and the conductive spacer, forming a source/drain region in the portions of the fin structures exposed from the dummy gate structure and the conductive spacer, disposing a dielectric structure over the substrate, removing the dummy gate structure to form a gate trench in the dielectric structure, the conductive spacer is exposed from sidewalls of the gate trench, disposing at least a gate dielectric layer over a bottom of the gate trench, and disposing a gate conductive structure in the gate trench, sidewalls of the gate conductive structure are in contact with the conductive spacer.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: I-SHENG CHEN, TZU-CHIANG CHEN, CHENG-HSIEN WU, LING-YEN YEH, CARLOS H. DIAZ
  • Patent number: 10361278
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Chao-Ching Cheng, Tzu-Chiang Chen, Chao-Hsien Huang