Patents by Inventor Tzu-Chiang Chen

Tzu-Chiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190067113
    Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 28, 2019
    Inventors: Hung-Li CHIANG, Chao-Ching CHENG, Chih-Liang CHEN, Tzu-Chiang CHEN, Ta-Pen GUO, Yu-Lin YANG, I-Sheng CHEN, Szu-Wei HUANG
  • Publication number: 20190067122
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Application
    Filed: January 8, 2018
    Publication date: February 28, 2019
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Publication number: 20190067121
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Hung-Li CHIANG, I-Sheng CHEN, Tzu-Chiang CHEN, Tung-Ying LEE, Szu-Wei HUANG, Huan-Sheng WEI
  • Patent number: 10170374
    Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang
  • Publication number: 20180360152
    Abstract: The helmet has a cap, and a turning assembly and a fastening device assembled on the cap. The helmet is formed as an integral whole and has a simplified and compact structure. A camera is mounted to the fastening device and is held by a lower holder and an upper holder of the turning assembly. A locking panel of the fastening device allows the camera to be easily and quickly mounted onto the cap via the fastening device or removed from the fastening device. With a locking member engaging in or disengaging from one of multiple engaging recesses of a corresponding guiding rod of the turning assembly, a position of the camera relative to the cap can be also easily and quickly adjusted.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 20, 2018
    Inventor: Tzu-Chiang Chen
  • Publication number: 20180364397
    Abstract: A long-wave infrared anti-reflective laminate includes a silicon substrate and an anti-reflective composite layer. The anti-reflective composite layer is disposed on the silicon substrate and has at least one first anti-reflective membrane. The at least one first anti-reflective membrane includes a first silicon nitride layer and a first silicon dioxide layer. The first silicon nitride layer is disposed between the silicon substrate and the first silicon dioxide layer. The thickness ratio of the first silicon nitride layer to the first silicon dioxide layer ranges from 175 to 225. The anti-reflective composite layer can be applied on the optical instrument to raise the transmitting rate of the silicon substrate. The transmitting rate of the long-wave infrared anti-reflective laminate is over 90% within the wave band from 8 ?m to 12 ?m.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 20, 2018
    Inventor: Tzu-Chiang Chen
  • Publication number: 20180366375
    Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: I-Sheng Chen, Tzu-Chiang Chen, Chih-Sheng Chang, Cheng-Hsien Wu
  • Publication number: 20180350971
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Publication number: 20180351436
    Abstract: A refrigerating machine having a detachable Hall element is provided with a cold heat exchange mechanism. The cold-heat exchange mechanism is driven by a driving assembly to generate a low temperature cooling zone at one end of the cold heat exchange mechanism. The driving assembly is composed of at least one rotor and a stator. After the power is input, the rotor can rotate a shaft to drive the cold-heat exchange mechanism to work. The driving assembly further has at least one Hall element and a circuit board on which the Hall element is mounted. Therefore, when the Hall element is damaged, the circuit board can be easily removed for replacement or repair.
    Type: Application
    Filed: January 30, 2018
    Publication date: December 6, 2018
    Inventor: Tzu-Chiang CHEN
  • Patent number: 10141310
    Abstract: A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Yu-Lin Yang, Chia-Cheng Ho, Hung-Li Chiang, Wei-Jen Lai, Tzu-Chiang Chen, Tsung-Lin Lee, Chih Chieh Yeh, Chih-Sheng Chang, Yee-Chia Yeo
  • Patent number: 10134640
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Chao-Ching Cheng, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10121870
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes semiconductor wires stacked over the fin structure. The semiconductor device structure further includes a gate stack over the fin structure. The semiconductor wires are surrounded by the gate stack. In addition, the semiconductor device structure includes source or drain structures over the fin structure and on opposite sides of the semiconductor wires. The semiconductor device structure also includes strain-relaxed buffer structures between the source or drain structures and the fin structure. The strain-relaxed buffer structures and the semiconductor wires have different lattice constants.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen
  • Publication number: 20180277448
    Abstract: A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath.
    Type: Application
    Filed: June 26, 2017
    Publication date: September 27, 2018
    Inventors: I-Sheng CHEN, Tzu-Chiang CHEN, Cheng-Hsien WU, Chih-Chieh YEH, Chih-Sheng CHANG
  • Patent number: 10062782
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Publication number: 20180151717
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: February 10, 2017
    Publication date: May 31, 2018
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Patent number: 9972545
    Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 15, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Chih Chieh Yeh, Cheng-Yi Peng, Tzu-Chiang Chen, Yee-Chia Yeo
  • Patent number: 9911850
    Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
  • Patent number: 9887100
    Abstract: Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Tsung-Lin Lee, Wei-Jen Lai, Chih Chieh Yeh
  • Publication number: 20170221772
    Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 3, 2017
    Inventors: Hung-Li Chiang, Chih Chieh Yeh, Cheng-Yi Peng, Tzu-Chiang Chen, Yee-Chia Yeo
  • Publication number: 20170125585
    Abstract: A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: HUNG-LI CHIANG, CHIH CHIEH YEH, CHENG-YI PENG, TZU-CHIANG CHEN, YEE-CHIA YEO