Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit.

Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract: A substrate having a metallic panel and an insulator is provided. The metallic panel comprises two patterned metallic layers. The two patterned metallic layers are disposed on the respective sides of the metallic panel and connected with each other. The metallic panel has an upper surface and a lower surface. The heat dissipating pathway between the upper and the lower surface is constructed using a metal. The insulator is positioned in the gaps between the patterned metallic layers.

Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

Abstract: A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive layer. Then, a dielectric layer is formed over the first conductive layer and the bump. A second conductive layer is formed over the dielectric layer. At least one blind hole is formed in the second conductive layer and the dielectric layer, passing through the second conductive layer and the dielectric layer to expose the top surface of the bump. A conductive material is filled in the blind hole, and the conductive material in the blind hole and the bump constitute a conductive post.

Abstract: A manufacturing process and an apparatus for printing imprint on defective board are provided. An automatic printing device is used for replacing operator, so as to reduce manpower and to increase the correctness and veracity of defect mark printing. The manufacturing process includes the following steps: first, an image sensor captures an image of a defect mark and transmits the image to a processing unit for data processing. Next, the data is compared, and an inkjet head is notified of the correct printing position to print ink on the customer identification mark of the printed circuit board.

Abstract: A method for fabricating a double-sided or multi-layer printed circuit board (PCB) by ink-jet printing that includes providing a substrate, forming a first self-assembly membrane (SAM) on at least one side of the substrate, forming a non-adhesive membrane on the first SAM, forming at least one microhole in the substrate, forming a second SAM on a surface of the microhole, providing catalyst particles on the at least one side of the substrate and on the surface of the microhole, and forming a catalyst circuit pattern on the substrate.

Abstract: An apparatus for metal plating on a substrate with through-holes includes a chamber that the substrate is disposed inside the chamber to be divided into two sections. A pressure generator and a pressure controller are connected to this and correspond to two sides of the substrate respectively. The pressure generator is used for pumping a electrolyte flowed parallel to the surface of the substrate into the chamber. The pressure controller is used for channeling the electrolyte off the chamber and controlling the pressure differences between the two sides of the substrate. So that the electrolyte flowed parallel to the surface of the substrate is pumped by the pressure generator and it passes several through-holes to control the thickness of metal plating on the.substrate and inner walls of the through-holes.

Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

Abstract: A method for inspecting and mending defects of photo-resist is provided. It includes the following steps. First, a substrate having at least one film is provided. Then, a patterned photo-resist layer is formed on the film. Next, an optical inspection procedure is performed to inspect whether the patterned photo-resist layer has defects or not. If the patterned photo-resist layer has defects, the defects are classified into gaps and protrusions and then the gaps and the protrusions are positioned. If the patterned photo-resist layer has defects such as gaps, an ink-jet printing method, for example, is performed on the patterned photo-resist layer to fill the gaps up. If the patterned photo-resist layer has defects such as protrusions, a laser method, for example, is performed on the patterned photo-resist layer to remove the protrusions. So the defects of the patterned photo-resist layer can be mended.

Abstract: A light emitting diode chip or chips array mounted on a substrate is surrounded by one or more side walls. The wall has an uneven reflecting surface to diverge the light emitted from the LED chip or chip array. The wall may have a triangular cross-section so that the emitted light diverges in all directions. When three double-sided reflecting walls surround three LED panels, the reflected light becomes omnidirectional hemispherically and can be used in a light bulb.

Abstract: A substrate having a metallic panel and an insulator is provided. The metallic panel comprises two patterned metallic layers. The two patterned metallic layers are disposed on the respective sides of the metallic panel and connected with each other. The metallic panel has an upper surface and a lower surface. The heat dissipating pathway between the upper and the lower surface is constructed using a metal. The insulator is positioned in the gaps between the patterned metallic layers.

Abstract: A substrate including a first patterned metallic layer, a second patterned metallic layer and an insulator is provided. One side of the first patterned metallic layer is connected to a corresponding side of the second patterned metallic layer. The first patterned metallic layer and the second patterned metallic layer are formed as a whole. The insulator fills the gaps in the first patterned metallic layer and the gaps in the second patterned metallic layer.

Abstract: A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive layer. Then, a dielectric layer is formed over the first conductive layer and the bump. A second conductive layer is formed over the dielectric layer. At least one blind hole is formed in the second conductive layer and the dielectric layer, passing through the second conductive layer and the dielectric layer to expose the top surface of the bump. A conductive material is filled in the blind hole, and the conductive material in the blind hole and the bump constitute a conductive post.

Abstract: A standardized or partial standardized circuit board core comprises at least a dielectric core layer and a plurality of conductive posts, in which the dielectric layer has a first surface and a related second surface. The conductive posts pass through the dielectric core layer and connect to the first and second surfaces of the dielectric layer respectively. The conductive posts are array arranged or arranged in a constant distance form in the dielectric core layer. Moreover, the standardized or partial standardized circuit board core further includes two conductive layers, which are covered on the first and second surfaces of the dielectric core layer.

Abstract: A light emitting diode chip or chips array mounted on a substrate is surrounded by one or more side walls. The wall has an uneven reflecting surface to diverge the light emitted from the LED chip or chip array. The wall may have a triangular cross-section so that the emitted light diverges in all directions. When three double-sided reflecting walls surround three LED panels, the reflected light becomes omnidirectional hemispherically and can be used in a light bulb.

Abstract: A printed circuit board thermal conductive structure comprises a thermal spreader layer having an embossed pattern formed on its surface, an adhesive glue layer formed over the thermal spreader, and a surface metallic layer attached to the thermal spreader and the glue layer. A portion of the surface metallic layer is in direct contact or almost direct contact with the thermal spreader. Furthermore, an additional external heat sink can be attached to thermal conductive structure to increase the efficiency of heat dissipation.

Abstract: The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached. The IC wire bonds within the cavity are sealed with an organic encapsulant.