Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.

Abstract: A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.

Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.

Abstract: A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract: A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.

Abstract: A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.

Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

Abstract: A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Abstract: A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.

Abstract: A package structure is provided that includes a metal plate; a semiconductor chip having an active surface, electrode pads disposed on the active surface, conductive bumps disposed on the electrode pads, and an inactive surface opposing the active surface and attached with the metal plate by a thermal conductive adhesive; an encapsulant formed on the metal plate for encapsulating a perimeter of the semiconductor chip, with the active surface of the semiconductor chip being exposed thereon; a first dielectric layer formed on the encapsulant and the active surface of the semiconductor chip, and having wiring trenches for exposing the conductive bumps; and a first wiring layer formed in the wiring trenches of the first dielectric layer and electrically connected to the conductive bumps. The wiring layer, through the electrical connection of the conductive bumps with the semiconductor chip prevents the use of bonding wires as a conductive pathway.

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract: A packaging substrate having a through-holed interposer embedded therein is provided, which includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer. By embedding the through-holed interposer in the molding layer and forming the built-up structure on the second surface of the molding layer, the present invention eliminates the need of a core board and reduces the thickness of the overall structure. Further, since the through-holed interposer has a CIE close to or the same as that of a silicon wafer, the structural reliability during thermal cycle testing is improved.

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract: A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer.

Abstract: A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract: An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated.

Abstract: A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.