Patents by Inventor Uday Shah

Uday Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME
    Publication number: 20140175575
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
  • ELECTRIC FIELD ENHANCED SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE
    Publication number: 20140177326
    Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Brian S. DOYLE, Charles C. KUO, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Uday SHAH
  • VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION
    Publication number: 20140166981
    Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Inventors: Brian S. DOYLE, Roza KOTLYAR, Uday SHAH, Charles C. KUO
  • METHOD FOR REDUCING SIZE AND CENTER POSITIONING OF MAGNETIC MEMORY ELEMENT CONTACTS
    Publication number: 20140167191
    Abstract: A method of centering a contact on a layer of a magnetic memory device. In one embodiment, a spacers is formed in an opening surrounding the upper layer and the contact is formed within the spacer. The spacer is formed from an anisotropically etched conformal layer deposited on an upper surface and into the opening.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 19, 2014
    Inventors: Brian S. Doyle, Yong Ju Lee, Charles C. Kuo, David L. Kencke, Kaan Oguz, Roksana Golizadeh Mojarad, Uday Shah
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 8749026
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES
    Publication number: 20140103397
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 17, 2014
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER
    Publication number: 20140084398
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Kaan OGUZ, Mark L. DOCZY, Brian DOYLE, Uday SHAH, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Robert S. CHAU
  • TECHNIQUES FOR FORMING NON-PLANAR GERMANIUM QUANTUM WELL DEVICES
    Publication number: 20140054548
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been-Yih Jin, Robert S. Chau
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20140035009
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 6, 2014
    Inventors: Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau
  • METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE
    Publication number: 20130334499
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 19, 2013
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yin Jin, Marko Radosavljevic, Willy Rachmady
  • Semiconductor device structures and methods of forming semiconductor structures
    Patent number: 8581258
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 12, 2013
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau
  • III-N MATERIAL STRUCTURE FOR GATE-RECESSED TRANSISTORS
    Publication number: 20130292698
    Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 7, 2013
    Inventors: Han Wui Then, Marko Radosavljevic, Uday Shah, Niloy Mukherjee, Ravi Pillarisetty, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Non-planar germanium quantum well devices
    Patent number: 8575596
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: November 5, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau
  • NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION
    Publication number: 20130264642
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 10, 2013
    Inventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Method of isolating nanowires from a substrate
    Patent number: 8525162
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 3, 2013
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same
    Patent number: 8519510
    Abstract: Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Uday Shah, Satyarth Suri, Ramanan V. Chebiam
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 8502351
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE
    Publication number: 20130062594
    Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 14, 2013
    Inventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady
  • Localized spacer for a multi-gate transistor
    Patent number: 8390040
    Abstract: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Ibrahim Ban, Uday Shah
  • NON-PLANAR GERMANIUM QUANTUM WELL DEVICES
    Publication number: 20130032783
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Application
    Filed: October 9, 2012
    Publication date: February 7, 2013
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Mark Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau