Patents by Inventor Uday Shah

Uday Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
    Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Forming high-k dielectric layers on smooth substrates
    Patent number: 7615441
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert S. Chau
  • Localized Spacer For A Multi-Gate Transistor
    Publication number: 20090267153
    Abstract: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.
    Type: Application
    Filed: July 10, 2009
    Publication date: October 29, 2009
    Inventors: Ibrahim Ban, Uday Shah
  • SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES
    Publication number: 20090218603
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Application
    Filed: May 8, 2009
    Publication date: September 3, 2009
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Method of patterning a film
    Patent number: 7579280
    Abstract: A method of patterning a thin film. The method includes forming a mask on a film to be patterned. The film is then etched in alignment with the mask to form a patterned film having a pair of laterally opposite sidewalls. A protective layer is formed on the pair of laterally opposite sidewalls. Next, the mask is removed from above the patterned film. After removing the mask from the patterned film, the protective layer is removed from the sidewalls.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Uday Shah, Robert S. Chau
  • REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY SILICIDATION
    Publication number: 20090206404
    Abstract: Reducing external resistance of a multi-gate device by silicidation is generally described. In one example, an apparatus includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a first surface, a second surface, and a third surface, the multi-gate fin also having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions wherein the source and drain regions of the multi-gate fin are fully or substantially silicized with a metal silicide, and a spacer dielectric material coupled to the first surface and the second surface wherein the spacer dielectric material substantially covers the first surface and the second surface in the source and drain regions.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Titash Rakshit, Robert S. Chau, Uday Shah
  • MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE
    Publication number: 20090206406
    Abstract: A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Inventors: Willy Rachmady, Uday Shah, Jack T. Kavalieros
  • Localized spacer for a multi-gate transistor
    Patent number: 7575976
    Abstract: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Ibrahim Ban, Uday Shah
  • REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    Publication number: 20090166741
    Abstract: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Uday Shah, Brian S. Doyle, Jack T. Kavalieros
  • Spacer patterned augmentation of tri-gate transistor gate length
    Publication number: 20090168498
    Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • Unity beta ratio tri-gate transistor static radom access memory (SRAM)
    Publication number: 20090166680
    Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Suman Datta, Jack Kavalieros, Brian S. Doyle, Uday Shah
  • REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN
    Publication number: 20090166742
    Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Inventors: Ravi Pillarisetty, Uday Shah, Titash Rakshit, Jack T. Kavalieros, Brian S. Doyle
  • Tri-gate patterning using dual layer gate stack
    Publication number: 20090170267
    Abstract: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Uday Shah, Brian S. Doyle, Jack T. Kavalieros, Been-Yih Jin
  • DEVICE WITH ASYMMETRIC SPACERS
    Publication number: 20090159936
    Abstract: An asymmetrical spacer adjacent a gate is formed. This asymmetry is used to form offset regions in a device.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Inventors: Uday Shah, Ibrahim S. Ban, Willy Rachmady
  • Nonplanar device with thinned lower body portion and method of fabrication
    Patent number: 7550333
    Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: June 23, 2009
    Assignee: Intel Corporation
    Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
  • Methods for patterning a semiconductor film
    Patent number: 7547637
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau, Brian S. Doyle
  • Selective surface exposure, cleans and conditioning of the germanium film in a Ge photodetector
    Patent number: 7547639
    Abstract: A method of protecting a sensitive layer from harsh chemistries. The method includes forming a first sensitive layer, forming a second layer upon the first layer, then forming a third layer over the second layer. The third layer is utilized as a mask during patterning of the second layer. During patterning, however, the second layer is only partially etched, thus leaving a buffer layer overlying the first layer. The third layer is completely removed while the buffer layer protects the first layer from the harsh chemicals that are utilized to remove the third layer. Then, the buffer layer is carefully removed down to the surface of the first layer.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Bruce A. Block, Uday Shah
  • METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS
    Publication number: 20090149012
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Application
    Filed: February 11, 2009
    Publication date: June 11, 2009
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
    Patent number: 7531437
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Jack Kavalieros, Mark Doczy, Uday Shah, Robert S. Chau
  • Nonplanar transistors with metal gate electrodes
    Patent number: 7528025
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 5, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Dovle, Jack Kavalleros, Mark Doczy, Uday Shah, Robert S. Chau