Abstract: An exemplary method and circuit for temperature nonlinearity compensation and trimming of a voltage reference are configured to provide for two-point independent trimming of each of the curvature coefficients within the Taylor approximation curve. A voltage reference circuit is configured with a translinear circuit having an input current source. The translinear circuit comprises a translinear unit having a plurality of output currents corresponding to the curvature coefficients of the Taylor row approximation curve, with the output currents coupled to a control input terminal of the voltage reference. During trimming, at a first nominal temperature, the input current source is trimmed to a zero value, and each of the curvature terms of the Taylor approximation will be equal to zero value.

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN)

Abstract: A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

Abstract: A method and device are configured for providing for both quick and accurate signal settling. A high accuracy component is configured in parallel with a high speed component. The high accuracy component may be an op-amp. The high speed component may be an OTA that is configured to be a non-linear OTA. Furthermore, an ADC is configured to internally provide both quick and accurate signal settling. For example, an ADC comprises an internal high speed OTA configured in parallel with a connected external op-amp. The OTA is configured to be a non-linear OTA.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transistor may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: A method and device are configured for providing for both quick and accurate signal settling. A high accuracy component is configured in parallel with a high speed component. The high accuracy component may be an op-amp. The high speed component may be an OTA that is configured to be a non-linear OTA. Furthermore, an ADC is configured to internally provide both quick and accurate signal settling. For example, an ADC comprises an internal high speed OTA configured in parallel with a connected external op-amp. The OTA is configured to be a non-linear OTA.

Abstract: A precision operational amplifier operating in single supply mode, including a single differential transistor input pair and a cascoded CMOS transistor pair, stabilizes the drain-to-source voltage of the input transistor pair to ensure a stable off-set voltage and increased power supply and common mode rejection. The precision amplifier biases the cascoded CMOS transistor pair in accordance with the stabilized drain-to-source voltage of the differential transistor input pair. Such biasing may take the form of body biasing or biasing the gates of the cascode CMOS transistor pair to ensure that the CMOS transistor pair remain in the active region of operation when the common mode supply voltage approaches zero.

Abstract: A multi-stage differential amplifier with rail-to-rail input may utilize an output stage including first and second low-voltage rated transistors and first and second high-voltage transistors. The first low-voltage rated transistor and the first high-voltage rated transister may be connected in series, and the second low-voltage rated transistor and the second high-voltage rated transistor may be connected in parallel. The low-voltage rated transistors are biased by signals provided by the input stage. In this way, the input stage controls the biasing of the low-voltage rated transistors in the output stage, thereby increasing the overall gain and speed of the amplifier system.

Abstract: An exemplary trimming circuit can be further simplified to include a single current source to provide for trimming of offset and temperature drift in a device, such as an op amp, voltage reference and the like. A single temperature-dependent current source is trimmed to a predetermined value, for example to zero, at a first temperature, and then the current from the temperature-dependent current source is used to trim output parameters, i.e., adjust the output variables, to a desired value at a second temperature. An exemplary trimming circuit comprises a temperature-dependent current source I(T), a current switch and a device to be, trimmed. The current switch is configured to suitably facilitate the trimming of the trimmed device through coupling of a fraction or multiple of the current signal from temperature-dependent current source I(T) to one or more offset-control terminals of the trimmed device.

Abstract: A precision operational amplifier operating in single supply mode, including a single differential transistor input pair and a cascoded CMOS transistor pair, stabilizes the drain-to-source voltage of the input transistor pair to ensure a stable off-set voltage and increased power supply and common mode rejection. The precision amplifier biases the cascoded CMOS transistor pair in accordance with the stabilized drain-to-source voltage of the differential transistor input pair. Such biasing may take the form of body biasing or biasing the gates of the cascode CMOS transistor pair to ensure that the CMOS transistor pair remain in the active region of operation when the common mode supply voltage approaches zero.

Abstract: A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage, on at least two different temperatures. The trimming circuit has a current source stage, having first and second current sources which are trimmed at a first temperature, in a first step, to balance the currents of the first and second current sources. The two current sources are configured to be selectively connected, in a second step and at the first temperature, to the offset-control terminal(s) of the input stage and thereby to trim the output of the input stage. The first and second current sources also have different temperature coefficients and are interchangeable with other current sources to facilitate changing, in a third step, the temperature coefficient of one of the two current sources to facilitate offset trimming at a second temperature.

Abstract: An exemplary trimming circuit can be further simplified to include a single current source to provide for trimming of offset and temperature drift in a device, such as an op amp, voltage reference and the like. A single temperature-dependent current source is trimmed to a predetermined value, for example to zero, at a first temperature, and then the current from the temperature-dependent current source is used to trim output parameters, i.e., adjust the output variables, to a desired value at a second temperature. An exemplary trimming circuit comprises a temperature-dependent current source I(T), a current switch and a device to be trimmed. The current switch is configured to suitably facilitate the trimming of the trimmed device through coupling of a fraction or multiple of the current signal from temperature-dependent current source I(T) to one or more offset-control terminals of the trimmed device.

Abstract: A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage, on at least two different temperatures. The trimming circuit has a current source stage, having first and second current sources which are trimmed at a first temperature, in a first step, to balance the currents of the first and second current sources. The two current sources are configured to be selectively connected, in a second step and at the first temperature, to the offset-control terminal(s) of the input stage and thereby to trim the output of the input stage. The first and second current sources also have different temperature coefficients and are interchangeable with other current sources to facilitate changing, in a third step, the temperature coefficient of one of the two current sources to facilitate offset trimming at a second temperature.

Abstract: A rail-to-rail class AB output stage includes a P-channel pull-up transistor (4) having a source coupled to a first supply rail voltage (V+), a gate coupled to a first input conductor (2) of the output stage, and a drain coupled to an output terminal (6) of the output stage. An N-channel pull-down transistor (5) includes a source coupled to a second supply rail voltage (GROUND), a gate coupled to a second input conductor (3) of the output stage, and a drain coupled to the output terminal (6). A P-channel first bias transistor (20) includes a source coupled to the first input conductor (2) and a drain coupled to the second input terminal (3). A first bias circuit coupled between the first and second supply rail voltages produces a first bias voltage (21) on a gate of the first bias transistor (20). A P-channel second bias transistor (10) includes a source coupled to be first input conductor (2).

Abstract: A voltage regulator is provided for taking an input voltage and providing a multiple of output voltages of differing voltage values. The voltage regulator includes a power switch and an inductor for providing inductor current to various output nodes. Control switches and a decision logic block are used to regulate the flow of inductor current to the output nodes, in accordance with predetermined values stored in the decision logic block. In one exemplary arrangement, the voltage regulator may provide a multiple of positive and negative voltage outputs. In another arrangement, the voltage regulator may provide a multiple of positive or negative voltage outputs or both.