Abstract: A different amplifier with rail-to-rail input including a single differential transistor pair utilizes a feedback circuit to control the threshold voltage of the differential transistor pair in accordance with the common mode voltage. The threshold voltage is controlled by adjusting the body bias coefficient with respect to the base to source voltage of the transistors.

Abstract: Over-current protection is accomplished in an output transistor (MP) of an electronic circuit wherein an input signal (Vgatedrive) Is Applying to a first conductor (19) coupled to a gate of the output transistor to cause an output current (Iout) to flow through the output transistor and an output terminal (11) of the electronic circuit. A limit voltage (VLIMIT) who is applied to an input (21) of a voltage clamping circuit (18) to cause a clamping current to flow in the first conductor (19) as needed to prevent the magnitude of the input signal (Vgatedrive) from being less than the magnitude of the limit voltage (VLIMIT) so that the output current (Iout) is limited to a maximum current limit determined by the limit voltage (VLIMIT).

Abstract: An input to a rail-to-rail, FET, operational amplifier having a transconductance that is constant throughout the operating range of the operational amplifier is presented. The input of an operational amplifier typically includes an input stage, a current source and a current transfer circuit, wherein the input stage comprises both N-type transistors and P-type transistors. The present application discloses the use of a duplicate of those elements: a proportional input stage, a proportional current source, and a proportional current transfer circuit, which together are used to emulate the operation of the input stage. By monitoring these proportional duplicates, one can determine when both input pairs are operating. When both input pairs are operating, a minimum selector circuit interfaces with the current transfer circuit to reduce the current supplying one of the input pair transistors, thus reducing the overall transconductance of the circuit.

Abstract: An input to a rail-to-rail, FET, operational amplifier having a transconductance that is constant throughout the operating range of the operational amplifier is presented. The input of an operational amplifier typically includes an input stage, a current source and a current transfer circuit, wherein the input stage comprises both N-type transistors and P-type transistors. The present application discloses the use of a duplicate of those elements: a proportional input stage, a proportional current source, and a proportional current transfer circuit, which together are used to emulate the operation of the input stage. By monitoring these proportional duplicates, one can determine when both input pairs are operating. When both input pairs are operating, a minimum selector circuit interfaces with the current transfer circuit to reduce the current supplying one of the input pair transistors, thus reducing the overall transconductance of the circuit.

Abstract: A voltage converter circuit includes a first transistor (M1) having a drain connected to receive an unregulated input voltage (Vin), a gate connected to receive a feedback control signal (4), and a source connected to a first conductor (5). An inductor (6) having a first terminal coupled to the first conductor (5) and a second terminal use connected to produce a regulated output voltage (Vout) on an output conductor (7). A feedback control circuit (190) coupled between the gate of the first transistor (M1) and the output conductor for regulating switching of the first transistor in response to the regulated output voltage (Vout).

Abstract: A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20).

Abstract: A differential input circuit (1) includes circuitry for generating slew boost currents to be supplied to an output stage of an operational amplifier. The differential input circuit (1) includes a differential current steering circuit including a first transistor (M2) having a gate coupled to receive a first input signal (Vin−), a second transistor (M3) having a gate coupled to receive a second input signal (Vin+), and a constant current source (20) coupled to sources of the first and second transistors, and providing first (4 or 6) and second (5 or 7) outputs of the differential input circuit coupled to the first (M2) and second (M3), respectively. A first slew current circuit is operated in response to the first input signal (Vin−) to produce a first slew boost current which is introduced into a current summing conductor (9) coupled to the sources of the first (M2) and second (M3) transistors and the constant current source (20).

Abstract: Bias circuitry of an electronic circuit is disabled by interrupting a compensated feedback loop in a bias control circuit that, when enabled, produces a predetermined bias voltage (VBIAS+) applied to the bias circuitry. A trickle charging current is conducted into a compensation capacitor of the feedback loop while the bias circuitry is disabled, to charge the compensation capacitor to a predetermined threshold voltage which causes the feedback loop and bias control circuit, when enabled, to produce the predetermined voltage needed by the bias circuitry to bias the CMOS operational amplifier for normal operation. Next, the feedback loop is enabled. Since the compensation capacitor is already precharged to the predetermined voltage, the bias circuitry of the CMOS operational amplifier is very quickly enabled from the disabled condition.

Abstract: An inductor current measurement circuit (25) accurately measures current supplied to an inductor (17) by a first transistor (2) and/or a second transistor (3). The first transistor (2) has a drain coupled to an input voltage conductor (8), a gate coupled to a switching signal (4), and a source coupled to a the first terminal of an inductor 17. A first sense transistor (7) has a gate and a drain connected to the gate and train, respectively, of the first transistor (2), and a source coupled to a first input of a first amplifier (13) and a drain of a third transistor (12) having a source coupled to a second supply voltage conductor (9), and a gate connected to the gate of a fourth transistor (15). The source of the fourth transistor (15) is connected to the second supply voltage conductive (9) and its drain is connected to an output terminal (18) and a second terminal coupled to the second supply voltage conductor (9). The first transistor (2) and second transistor (3) are included in a DC-DC converter.

Abstract: A class AB output stage includes an amplifying stage adapted to produce first (9) and second (10) output signals which incrementally increase and decrease in response to an incremental increase and decrease, respectively, of a first input signal (Iin1) and/or a second input signal (Iin2) A gate of a pull-up transistor (14) is coupled to receive the second signal (10), and a gate of a pull-down transistor (12) is coupled to receive the first signal (9). A first feedback circuit includes a first current sensing transistor (11) having a gate and source connected to the gate and source, respectively, of the pull-down transistor (12) and a drain coupled to a first control input (7) of the amplifying stage and operative to increase the gate voltage of the first current sensing transistor (11) only until its drain current increases to a first predetermined value representative of a minimum desired quiescent current in the pull-down transistor (12).

Abstract: An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32).

Abstract: A rail-to-rail differential amplifier includes first and second input terminals, and an output terminal and an input stage including differentially connected N-channel first and second input transistors, and differentially connected P-channel third and fourth input transistors. A P-channel first cascode transistor has a source coupled to a first supply voltage to the drain of the first input transistor. An N-channel cascode transistor has a source coupled by a second resistive element to a second supply voltage and to the drain of the third input transistor. A first gain boost amplifier has an output coupled to a gate of the first cascode transistor, a first input coupled to the source of the first cascode transistor and the drain of the first input transistor, and a second input coupled to a drain of the second input transistor and a bias control circuit.

Abstract: An operational amplifier includes an input stage (13) receiving an input signal (Vin) and having first (14) and second (16) output terminals, and also includes an output stage (10) having a pull-up transistor (M11) and a pull-down transistor (M2). The pull-up transistor has a source coupled to a first supply voltage (VDD), a gate coupled to the first output terminal (14), and a drain coupled to an output conductor (22) conducting an output signal (Vout). The pull-down transistor (M2) has a source coupled to a second supply voltage (VSS), a gate coupled to the second output terminal (16), and a drain coupled to the output conductor (22). An AB control circuit (20) is coupled between the gates of the pull-up transistor and a pull-down transistor.

Abstract: A voltage regulator (1) and includes a first switch (S1) coupled between an input conductor (2) and a first terminal (4) of an inductor (5), a second switch (S2) coupled between the first terminal of the inductor and a common conductor (3), a third switch coupled between an output conductor (7) and a second terminal (6) of the inductor, and a fourth switch (S4) coupled between the second terminal of the inductor and the common conductor (3). The voltage regulator is operated in a mixed buck-boost mode by producing a first signal (V32) representative of the difference between an output voltage (VOUT) produced on the output conductor (7) by the voltage regulator and a reference voltage. A second signal (IMEAS) is produced to represent the current through the inductor (5). A third signal (V68) is produced to represent a combination of the first signal and the second signal. A pulse width modulated error signal (PWM) is produced by comparing the third signal (V68) to a reference voltage.

Abstract: A differential amplifier includes a rail-to-rail input stage including differentially coupled first (13) and second (14) P-channel input transistors, and differentially coupled third (17) and fourth (18) N-channel input transistors. The drains of the first and second input transistors are coupled to a first folded cascode circuit which includes first (25) and second (26) P-channel cascode transistors. The drains of the third and fourth input transistors are coupled to a second folded cascode circuit which includes third (36) and fourth (37) N-channel cascode transistors. An output stage includes a P-channel pull-up transistor and an N-channel pull-down transistor and a class AB bias circuit coupled between the gates thereof. The gates of the first (25) and third (36) cascode transistors are coupled to first and second reference voltages, respectively.

Abstract: An operational amplifier output circuit having a low, stable quiescent current includes an input stage (22) receiving an input voltage (v.sub.in ") and producing first (v.sub.1) and second (v.sub.2) signals. An output stage (23) includes a pull-up transistor (1) and a pull-down transistor (2), a base of the pull-up transistor (1) receiving the first signal (v.sub.1). An emitter of the pull-up transistor (1) is coupled by an output conductor (30) to a collector of the pull-down transistor (2). A base of the pull-down transistor is coupled to receive the second signal (v.sub.2), and an emitter of the pull-down transistor (2) is coupled to a second reference voltage conductor (GND). A feedback stage (24) includes a first sensing circuit (36) coupled to the pull-up transistor 1 and produces a third signal (v.sub.3) representing a collector current of the pull-up transistor (1), a second sensing circuit (37) coupled to the pull-down transistor (2) and producing a fourth signal (v.sub.

Abstract: A three-stage amplifier including first, second, and third sequentially coupled stages is compensated without use of compensation capacitors, by applying an input signal to an input of the first stage and a first input of a first feed-forward stage, coupling an output signal of the first feed-forward stage to an output of the second stage, the second stage having an input coupled to an output of the first stage, coupling an output signal of the first stage to an input of a second feed-forward stage, coupling an output of the second feed-forward stage to an output of the third stage, coupling the input signal to an input of a third feed-forward stage, and coupling an output of the third feed-forward stage to the output of the third stage.

Abstract: A precision voltage level shift circuit includes an emitter follower input circuit including a lateral PNP transistor having a base receiving an input voltage, and an emitter coupled to both an output terminal and a first current source. JFET is coupled between a collector of the input transistor and a first supply voltage conductor. A second PNP transistor has a base coupled to the collector of the first transistor and an emitter coupled to a second current source. A differential amplifier has a first input coupled to the output terminal, a second input coupled to the emitter of the second transistor, and an output coupled to the load element. The differential amplifier operates to maintain the voltage drop across the JFET at a level such that the emitter of the second PNP transistor is equal to the voltage of the emitter of the lateral PNP transistor to thereby maintain the collector-emitter voltage thereof at a constant value.