Abstract: A method for sorting nanotubes and forming devices based upon selective nanotube types is provided. The disclosure provides methods of sorting semiconducting nanotubes useful in the formation of field effect transistors, diodes, and resistors. The disclosure also provides methods of sorting metallic nanotubes useful in the formation of interconnect devices.

Abstract: The present invention relates to a cobalt electroless plating bath composition and method of using it for microelectronic device fabrication. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.

Abstract: An apparatus for electroless spray deposition of a metal layer on a substrate, e.g., a Co shunt or barrier layer on a Cu layer on a semiconductor wafer, includes a processing chamber to hold the substrate, the processing chamber including at least one section movable between an open position to allow the substrate to be introduced into and removed from the processing chamber and a closed position to seal the processing chamber to allow for pressurization of the processing chamber. The processing chamber has an inlet to provide pressurizing gas, an exhaust line to exhaust pressurizing gas, a pressure regulator to regulate pressure there-within, and a sprayer to spray an electroless plating solution onto the substrate. A method for electroless spray deposition includes providing the in a processing chamber, sealing the processing chamber, pressurizing the processing chamber, regulating the pressure, and spraying an electroless plating solution onto the substrate.

Abstract: Formation of an interconnect circuit feature having a metal and an electropositive dopant. The interconnect feature may contain an accumulation of the electropositive dopant at interface boundaries of the interconnect feature to reduce electromigration of the metal during operation. In a method the interconnect feature may be heated to drive a portion of the electropositive dopant to the interfaces.

Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Abstract: A composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a metal matrix. The composite carbon nanotube structure may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: A process for forming electroless metal conductors in an integrated circuit as part of, for example, a damascene or dual damascene process without the use of a seed layer, is described. A catalyst is used to cause the via openings and trenches to be filled from the bottom up, thereby minimizing voids.

Abstract: Formation of an interconnect circuit feature having a metal and an electropositive dopant. The interconnect feature may contain an accumulation of the the electropositive dopant at interface boundaries of the interconnect feature to reduce electromigration of the metal during operation. In a method the interconnect feature may be heated to drive a portion of the electropositive dopant to the interfaces.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: A method of forming a copper interconnect, comprising forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer. The copper-noble metal alloy improves the electrical characteristics and reliability of the copper interconnect.

Abstract: An electroless cobalt plating solution, comprising cobalt ions, at least one reducing agent, and an ammonia-free complexing/buffering agent (such as glycine, triethanolamine, and tris(hydrozymethyl)aminoethane). The electroless cobalt plating solution may be used in the fabrication of variety of structures including copper diffusion barriers and salicides contact in the manufacture of microelectronic dice.

Abstract: A method of treating an electroless plating waste is provided. The waste is contained and an ability of a reducing agent to reduce a metal of the waste is decreased, for example by adding a stabilizing chemical or by exposing the waste to an anode to which a positive voltage is applied. Poisonous and explosive gases evolve from the waste, which are vented. Upon completion, the waste is drained.

Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Abstract: Formation of an interconnect circuit feature having a metal and an electropositive dopant. The interconnect feature may comprise an accumulation of the electropositive dopant at interface boundaries of the interconnect feature to reduce electromigration of the metal during operation. A method may comprise heating the interconnect feature to drive a portion of the electropositive dopant to the interfaces.

Abstract: A method including forming at least two monocrystalline layers of different resistance values in a surface of a substrate, protecting an area of the surface of the substrate, forming a trench in a non-protect area of the surface of the substrate to a body of the substrate, anodically etching a portion of the substrate body; and oxidizing the anodically etched portion of the substrate body. An apparatus including a device substrate having an active area including an epitaxial layer over an oxidized portion of the body of the substrate, wherein the active area is defined by a trench formed in the substrate to a point beyond the epitaxial layer; and at least one device formed in or on the active area of the device substrate.

Abstract: The present invention relates to a cobalt electroless plating bath composition and method of using it for microelectronic device fabrication. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.