Patents by Inventor Van Le

Van Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220383150
    Abstract: This disclosure describes methods, non-transitory computer readable storage media, and systems that provide a platform for on-demand selection of machine-learning models and on-demand learning of parameters for the selected machine-learning models via cloud-based systems. For instance, the disclosed system receives a request indicating a selection of a machine-learning model to perform a machine-learning task (e.g., a natural language task) utilizing a specific dataset (e.g., a user-defined dataset). The disclosed system utilizes a scheduler to monitor available computing devices on cloud-based storage systems for instantiating the selected machine-learning model. Using the indicated dataset at a determined cloud-based computing device, the disclosed system automatically trains the machine-learning model.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Nham Van Le, Tuan Manh Lai, Trung Bui, Doo Soon Kim
  • Publication number: 20220325240
    Abstract: Cartridges for manufacturing a population of cells suitable for formulation as a cellular therapeutic are disclosed herein, along with systems and instruments for operating the cartridges and performing methods to generate the population of cells suitable for formulation as a cellular therapeutic. The population of cells suitable for formulation as a cellular therapeutic can be immunological cells, such as T lymphocytes, including endogenous T cells (ETCs), tumor infiltrating lymphocytes (TILs), CAR T-cells, TCR engineered T-cells, or otherwise engineered T-cells. The systems and methods can be largely automated.
    Type: Application
    Filed: January 12, 2022
    Publication date: October 13, 2022
    Inventors: Andrew W. McFarland, Peter J. Beemiller, Guido K. Stadler, Alexander J. Mastroianni, Joshua J. Cardiel Rivera, Darcy K. Kelly-Greene, Jonathan Cloud Dragon Hubbard, Natalie C. Marks, Long Van Le, Ke-Chih Lin
  • Publication number: 20220275267
    Abstract: Provided are methods for modifying the permeability of subterranean formations for the purposes of selectively reducing excessive production of water and aqueous fluids in oil and gas wells, wherein the methods utilize an emulsion containing a copolymer, which is typically prepared in an aqueous salt media.
    Type: Application
    Filed: July 23, 2019
    Publication date: September 1, 2022
    Applicant: RHODIA OPERATIONS
    Inventors: Chee Fei Chin, Zhihua Zhang, Zhenxing Cheng, Ahmed Rabie, Hoang Van Le
  • Publication number: 20220267255
    Abstract: Disclosed are substantially pure L-y-methyleneglutamine, L-y-methyleneglutamic acid, and/or amide derivatives, and methods of use thereof. In particular, the presently disclosed subject matter relates to L-y-methyleneglutamine, L-y-methyleneglutamic acid, and/or amide derivatives thereof, and methods of treating cancer. The method comprises administering one or more substantially pure L-y-methyleneglutamine, L-y-methyleneglutamic acid, and/or amide derivatives to a subject in need thereof.
    Type: Application
    Filed: July 13, 2020
    Publication date: August 25, 2022
    Inventors: Hoang Van LE, Md. Imran HOSSAIN
  • Publication number: 20220253119
    Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Inventors: Rajashree Baskaran, Maruti Gupta Hyde, Min Suet Lim, Van Le, Hebatallah Saadeldeen
  • Patent number: 11373320
    Abstract: A camera with a field of view of a shelf may acquire images of items on the shelf at subsequent times. An analysis of each image yields a set of estimated locations of the items on the shelf. Based on a working volume of the shelf, a subset of valid estimated locations of the items at the shelf may be determined. Thereafter, a count of the items on the shelf at a particular time may be determined using the subset of valid estimated item locations. By comparing the count of items at the shelf at two subsequent times, a change in quantity of the items on the shelf may be determined. Interaction data may be generated in response to detecting the change in quantity of items at the shelf.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 28, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Vuong Van Le, Joseph Patrick Tighe
  • Publication number: 20220170254
    Abstract: A toilet seal for sealing between a plumbing fixture discharge and a waste drainpipe outlet is described. The toilet seal comprises a flange member having an inwardly extending flexible lip. A flexible sleeve extends downwardly from the flange member. The toilet seal further includes a compressible member having an upper surface disposed adjacent to a lower surface of the flange member. The compressible member further has a lower surface and a plurality of ridges extend downwardly from the lower surface of the compressible member.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Eduardo Coronado, Pedro Gonzalez, Adam Robert Sampson, Tuan Van Le, Krishnaditya Arkalgud
  • Patent number: 11348909
    Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Maruti Gupta Hyde, Nageen Himayat, Linda Hurd, Min Suet Lim, Van Le, Gayathri Jeganmohan, Ankitha Chandran
  • Patent number: 11320883
    Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Maruti Gupta Hyde, Min Suet Lim, Van Le, Hebatallah Saadeldeen
  • Publication number: 20220127523
    Abstract: The present disclosure provides polymeric systems that exhibit enhanced viscosity and proppant transport properties while providing enhanced particle dispersion capabilities.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 28, 2022
    Applicant: RHODIA OPERATIONS
    Inventors: Genyao Lin, Christopher Smith, Hoang Van Le, Qi Qu
  • Publication number: 20220122983
    Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: Intel Corporation
    Inventors: Yih Wang, Abhishek Sharma, Van Le
  • Patent number: 11268270
    Abstract: A toilet seal for sealing between a plumbing fixture discharge and a waste drainpipe outlet is described. The toilet seal comprises a flange member having an inwardly extending flexible lip. A flexible sleeve extends downwardly from the flange member. The toilet seal further includes a compressible member having an upper surface disposed adjacent to a lower surface of the flange member. The compressible member further has a lower surface and a plurality of ridges extend downwardly from the lower surface of the compressible member.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 8, 2022
    Assignee: COFLEX S.A. DE C.V.
    Inventors: Eduardo Coronado, Pedro Gonzalez, Adam Robert Sampson, Tuan Van Le, Krishnaditya Arkalgud
  • Patent number: 11257956
    Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Gilbert Dewey, Van Le, Jack Kavalieros, Tahir Ghani
  • Publication number: 20220052200
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 17, 2022
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
  • Publication number: 20220037281
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Application
    Filed: October 13, 2021
    Publication date: February 3, 2022
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • Patent number: 11222895
    Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek Sharma, Van Le
  • Publication number: 20210408291
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Publication number: 20210401655
    Abstract: A system for positioning a patient before, during or after a medical procedure can include an arm assembly and a surgical drape for use with the arm assembly. The surgical drape can be configured to be placed around a surgical site where an operative procedure is to be conducted. The surgical drape includes a transparent viewing window, multiple handle covers, and an expandable opening on the top side of the surgical drape. Additionally, the surgical drape may also include adhesive components on the bottom side of the drape that may be independently removed in order to affix the drape around a surgical site.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: Mark Edward DeSilets, Stephan John Schmid, Vincent Hodges, Peter Thien Van Le
  • Publication number: 20210408002
    Abstract: An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Travis W. LaJoie, Abhishek A. Sharma, Van Le, Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Juan G. Alzate-Vinasco
  • Publication number: 20210395988
    Abstract: A fluid valve with a modular and/or replaceable fluid control assembly is disclosed, and is configured and arranged to require maintenance over a product life of the fluid valve. The modular and/or replaceable fluid control assembly includes at least one portion including a setting or presetting configured and arranged to control fluid flow behavior in the fluid valve. The setting or presetting is useable to control fluid flow in the modular and/or replaceable fluid control assembly after an upgrade or replacement of at least a portion of the modular and/or replaceable fluid control assembly. Further, the setting or presetting enables the modular and/or replaceable fluid control assembly to retain the fluid flow behavior following one or more upgrades or replacements of one or more portions of the modular and/or replaceable fluid control assembly.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 23, 2021
    Inventors: Tuan Van Le, Joseph Unkyung Han, Salvador Pena