Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

Abstract: In one embodiment, a device identifies, from image data captured by one or more cameras of a physical location, a focal point of interest and people located within the physical location. The device forms a set of nodes whereby a given node represents one or more of the identified people located within the physical location. The device represents a person queue as an ordered list of nodes from the set of nodes and adds a particular one of the set of nodes to the list based on the particular node being within a predefined distance to the focal point of interest. The device adds one or more nodes to the list based on the added node being within an angle and distance range trailing a forward direction associated with at least one node in the list. The device provides an indication of the person queue to an interface.

Abstract: Bandgap reference diodes and bandgap reference circuits are used to provide voltage references for a wide range of integrated circuit (IC) functions. Many bandgap reference diodes are fabricated directly on the substrate surface during the front-end-of-line (FEOL), and require a significant substrate footprint. Embodiments described herein are directed to bandgap reference diodes comprised of thin film transistors and methods of forming the same. The bandgap reference diodes described herein need not be fabricated during the FEOL, and can instead be formed during the back-end-of-line (BEOL) metallization workflow, freeing the substrate surface for other devices.

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

Abstract: Embodiments include a fluid valve with a modular and/or replaceable fluid control assembly configured and arranged to require maintenance over a product life of the fluid valve. The modular and/or replaceable fluid control assembly includes at least one portion including a setting or presetting configured and arranged to control fluid flow behavior in the fluid valve. The setting or presetting is useable to control fluid flow in the modular and/or replaceable fluid control assembly after an upgrade or replacement of at least a portion of the modular and/or replaceable fluid control assembly. Further, the setting or presetting enables the modular and/or replaceable fluid control assembly to retain the fluid flow behavior following one or more upgrades or replacements of one or more portions of the modular and/or replaceable fluid control assembly.

Abstract: A prosthetic heart valve for implant in a human. The valve includes a wireform with undulating inflow cusps and outflow commissure posts to which flexible leaflets attach and coapt in a flow area. Each leaflet may drape over the top of the wireform in the cusp area, but have tabs that each extend underneath the wireform at the commissure posts to be secured along with a tab of an adjacent leaflet. The prosthetic heart valve may also be a dual-wire wireform, with the leaflets sandwiched therebetween. One wireform may be larger than the other, with the leaflets extending over the smaller wireform. The smaller wireform may have commissures that bend radially outward from the larger wireform to provide structure to which the leaflet tabs attach.

Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract: A computerized process can be used to create and distribute a durable coupon token redeemable with a company agreeing to permit a user redeem the durable coupon token for a discount. The process includes, within a computerized processor, operating programming configured to create the durable coupon token. The durable coupon token includes a digital security key associated with the durable coupon token configured to provide transferrable ownership of the durable coupon token. The process further includes distributing the durable coupon token to a consumer. The durable coupon token is configured to enable the consumer to claim the discount with the company.

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

Abstract: Images of a fixture such as a shelf holding items may be acquired by cameras and processed to count the quantity of items at the fixture. A top of an item is determined in the image. Given information about the items designated for stowage at the fixture and the location of the top, a three-dimensional (3D) bounding box indicative of a volume is determined relative to the fixture. Bounding boxes which extend outside the boundaries of the fixture are disregarded. Remaining bounding boxes may then be analyzed to determine a measured height of the item(s) in a stack. The measured height may be divided by a per-item height to determine a quantity of items in the stack. The quantities in multiple stacks may be summed to determine a quantity at the fixture.

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

Abstract: The present disclosure provides polymeric systems that are able to undergo fast hydration and are useful for maintaining particle dispersions for extended periods of time.

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract: A toilet seal for sealing between a plumbing fixture discharge and a waste drainpipe outlet is described. The toilet seal comprises a flange member having an inwardly extending flexible lip and one or more raised ridges defining an annular seal extending upwardly from an upper surface of the flange member. The toilet seal further includes a radiused wall extending downwardly from the flange member, which cooperates with the flange member to define a cavity for receiving a compressible member. The toilet seal further comprises a flexible sleeve extending downwardly from the radiused wall. Related methods are described.

Abstract: Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

Abstract: In one embodiment, a device identifies, from image data captured by one or more cameras of a physical location, a focal point of interest and people located within the physical location. The device forms a set of nodes whereby a given node represents one or more of the identified people located within the physical location. The device represents a person queue as an ordered list of nodes from the set of nodes and adds a particular one of the set of nodes to the list based on the particular node being within a predefined distance to the focal point of interest. The device adds one or more nodes to the list based on the added node being within an angle and distance range trailing a forward direction associated with at least one node in the list. The device provides an indication of the person queue to an interface.

Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.