Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Abstract: Examples disclosed herein relate to security actions that can be taken at a network appliance based on a received copy of a neighbor discovery packet. The neighbor discovery packet copy is received on a control plane of a network that originated at a port on a data plane of the network. The neighbor discovery packet copy includes identification information including an internet protocol address, a media access control address, and information about the port. The identification information is compared to a binding state table to determine that the internet protocol address and the media access control address match the binding state table, but the port does not match a previous port on the binding state table for the internet protocol address. A security action is performed.

Abstract: In various embodiments, the present invention provides a process for separating target proteins from non-target proteins in a sample comprising increasing the concentration of the target proteins and non-target proteins in the sample and subsequently delivering the concentrated sample to a chromatography device. In other embodiments, the invention relates to a process for increasing the capacity of a chromatography device for a target protein by delivering a concentrated sample comprising the target protein to a chromatography device.

Abstract: Examples disclosed herein relate to providing a failover in a MACsec capable device. In an example, a determination may be made on a Media Access Control (MAC) Security (MACsec) capable device, whether a primary management engine that manages a protocol related to MACsec standard on the MACsec capable device has failed. In response to a determination that the primary management engine has failed, a secondary management engine in the MACsec capable device may create a Connectivity Association (CA) between the MACsec capable device and a peer MACsec capable device by performing an IEEE 802.1X re-authentication with the peer MACsec capable device within MACsec Key Agreement (MKA) lifetime. The MKA lifetime may refer to a period during which no MACsec Key Agreement Protocol Data Unit (MKPDU) is received by the peer MACsec capable device from the MACsec capable device.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Abstract: In various embodiments, the present invention provides a process for separating target proteins from non-target proteins in a sample comprising increasing the concentration of the target proteins and non-target proteins in the sample and subsequently delivering the concentrated sample to a chromatography device. In other embodiments, the invention relates to a process for increasing the capacity of a chromatography device for a target protein by delivering a concentrated sample comprising the target protein to a chromatography device.

Abstract: A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.

Abstract: Processor architectures and associated methods provide interruptible, instruction-based trigonometric function computation based on CORDIC iterations, receiving and outputting floating-point values (e.g., 64-bit). The architectures and methods can provide multiple CORDIC-like iterations in as little as a single CPU processing cycle to provide an overall faster execution of trigonometric operations while having zero additional overhead for service of time-critical interrupts. Post interrupt service, a CORDIC operation can be resumed from where it was interrupted.

Abstract: Examples disclosed herein relate to providing a failover in a MACsec capable device. In an example, a primary management engine that runs a protocol of MACsec standard in a MACsec capable device may determine whether a parameter related to a protocol of MACsec standard on the MACsec capable device has changed. In response to the determination that the parameter has changed, primary management engine may synchronize data related to the parameter to a secondary management engine, which acts as a failover component for the primary management engine. In response to a determination that the primary management engine has failed, secondary management engine may recreate the latest state of the protocol of MACsec standard in the MACsec capable device prior to the failure of the primary management engine, based on the data related to the parameter.

Abstract: Examples disclosed herein relate to security actions that can be taken at a network appliance based on a received copy of a neighbor discovery packet. The neighbor discovery packet copy is received on a control plane of a network that originated at a port on a data plane of the network. The neighbor discovery packet copy includes identification information including an internet protocol address, a media access control address, and information about the port. The identification information is compared to a binding state table to determine that the internet protocol address and the media access control address match the binding state table, but the port does not match a previous port on the binding state table for the internet protocol address. A security action is performed.

Abstract: A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Abstract: Systems and methods for normalizing and searching electronic data, such as chemical material property data, are disclosed. In one embodiment, a method includes receiving electronic data from a source. The electronic data is formatted in a source format. The method further includes converting the source data into a normalized format, and storing normalized electronic data in levels of a nested model. The method further includes receiving a search or browse query directed toward normalized properties in a first level of the nested model or a second level of the nested model, in any non-hierarchical order. The method also includes searching the nested model and causing for display on an electronic display one or more entities satisfying the query and maintaining the integrity of all parameters of the query across all selected properties queried in any non-hierarchical order.

Abstract: Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.