Abstract: An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation device can be configured to emulate blocks of memory on a target processor system. Each block of memory responds to three different memory buses and can receive up the three simultaneous memory requests. Arbitration circuitry selects the highest priority memory request for service on each cycle. Each memory block is configured to respond to a block of addresses beginning at a selected starting address. Two blocks of memory can be linked to form a single merged block of memory in which both arbitration circuits operate in lock step by masking a most significant address bit of the block of address selected for the memory block.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: A circuit determining whether a present value transmitted on a bus equals any of several desired values. The circuit may contain a monitor random access memory (RAM) and a monitor circuit. The bits of a desired value at a second set of positions are stored in a location (of the monitor RAM) having an address formed by the bits of the desired value at the a first set of positions. When a value (“present value”) is transmitted on the bus, the bits of the present value at the first set of positions are provided as an address to the monitor RAM, which generates the bits stored in the addressed location as output. The monitor circuit compares the output of monitor RAM with the bits of the present value at the second set of positions to generate a result. The result indicates if the a desired value has occurred on the bus.

Abstract: A processor core is provided that is a programmable digital signal processor (DSP). The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags from the tag circuitry.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.