Patents by Inventor Venkatraghavan Bringivijayaraghavan

Venkatraghavan Bringivijayaraghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545198
    Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
    Type: Grant
    Filed: May 30, 2021
    Date of Patent: January 3, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran, Igor Arsovski
  • Patent number: 11302415
    Abstract: Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 12, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Sreejith Chidambaran, Prasad Vernekar
  • Publication number: 20210287725
    Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
    Type: Application
    Filed: May 30, 2021
    Publication date: September 16, 2021
    Inventors: Venkatraghavan BRINGIVIJAYARAGHAVAN, Arjun Sankar, Sreejith Chidambaran, Igor Arsovski
  • Publication number: 20210192336
    Abstract: Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Marvell International Ltd.
    Inventors: Deepak I. Hanagandi, Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi
  • Publication number: 20210183460
    Abstract: Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Applicant: Marvell International Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Sreejith Chidambaran, Prasad Vernekar
  • Patent number: 11024347
    Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 1, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran, Igor Arsovski
  • Publication number: 20210118477
    Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Inventors: Venkatraghavan Bringivijayaraghavan, Arjun Sankar, Sreejith Chidambaran, Igor Arsovski
  • Patent number: 10964357
    Abstract: Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 30, 2021
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Anoop Delampady, Puneet Suri
  • Publication number: 20210034567
    Abstract: A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi, Deepak I. Hanagandi, Igor Arsovski
  • Publication number: 20200342918
    Abstract: Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Anoop Delampady, Puneet Suri
  • Patent number: 10600474
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 24, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10522217
    Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi, George M. Braceras
  • Patent number: 10510384
    Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, George M. Braceras
  • Publication number: 20190279708
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Patent number: 10395700
    Abstract: Embodiments of the present disclosure provide a circuit structure including: first PMOS and second PMOS each including a gate, source, and drain; wherein sources of first and second PMOS are coupled to first voltage source, gate of first PMOS is cross coupled to drain of second PMOS, gate of second PMOS is cross coupled to drain of first PMOS, drain of the first PMOS is coupled to first bit-line node, and wherein drain of second PMOS is coupled to second bit-line node; write bit-switch having first NMOS coupled to first bit-line node and second NMOS coupled to second bit-line node, wherein first and second NMOS of write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and ground.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Sreenivasa Chaitanya Kumar Vavilla
  • Patent number: 10381069
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Publication number: 20190244658
    Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 8, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sreenivasula Reddy Dhani Reddy, Sreejith Chidambaran, Binu Jose, Venkatraghavan Bringivijayaraghavan
  • Publication number: 20190147924
    Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Venkatraghavan BRINGIVIJAYARAGHAVAN, George M. BRACERAS
  • Patent number: 10217507
    Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Sreejith Chidambaran, Igor Arsovski
  • Patent number: 10199095
    Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dhani Reddy Sreenivasula Reddy, Venkatraghavan Bringivijayaraghavan, Vinay Bhat Soori