Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.

Abstract: A circuit includes a memory array having memory cells and bitlines. A write driver is connected to the bitlines through column select transistors. A write assist circuit is connected to the write driver. The write assist circuit includes a common boost node, negative boost transistors, and a keeper transistor. The negative boost transistors are connected from the digit lines to the common boost node. The negative boost transistors selectively pull the bitlines of a selected cell of the memory array to ground during a write operation to the selected cell of the memory array. The write assist circuit may include a first negative boost transistor connected from a first digit line to the common boost node, a second negative boost transistor connected from a second digit line to the common boost node, and a keeper transistor connected from the common boost node to ground.

Abstract: The present disclosure relates to a structure which includes a dual write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line of the memory cell array.

Abstract: Embodiments of the present disclosure provide a circuit structure including: a circuit driven by first and second sense amplifier (SA) output; a first driver having a first PMOS coupled to a node and to a pair of serially coupled NMOSs, wherein the first SA output is coupled to the first PMOS and the first NMOS of the first driver; a second driver having a second PMOS coupled to a node and a pair of coupled NMOSs, wherein the second SA output is coupled to the second PMOS and second NMOS of the second driver; a first and second supply PMOS, wherein first supply PMOS is coupled to the node of the first driver and to the second supply PMOS and first NMOS of the second driver, and wherein the second supply PMOS is coupled to node of second driver and to the first supply PMOS and second NMOS of first driver.

Abstract: The present disclosure relates to a structure which includes a dual write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line of the memory cell array.

Abstract: The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections. Other apparatuses and methods are disclosed.

Abstract: The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

Abstract: A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

Abstract: The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use. The multiplexed latch includes: a first latch structured to receive a data signal D0 and comprising a plurality of inverters which receive a respective input clock signal; and a second latch signal structured to receive a data signal D1 and comprising a plurality of inverters which receive a respective input clock signal.

Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.

Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.

Abstract: Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches.

Abstract: The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use. The multiplexed latch includes: a first latch structured to receive a data signal D0 and comprising a plurality of inverters which receive a respective input clock signal; and a second latch signal structured to receive a data signal D1 and comprising a plurality of inverters which receive a respective input clock signal.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.