Patents by Inventor Venkatraman Iyer

Venkatraman Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11197322
    Abstract: Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 7, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Venkatraman Iyer, Dixon Chen, John Junling Zang, Michael Rentschler
  • Patent number: 11160794
    Abstract: The present disclosure relates generally to compounds and pharmaceutical compositions for increasing glycosylation and treating congenital disorders of glycosylation.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Maggie's Pearl, LLC
    Inventors: Ethan Oren Perlstein, Jessica Lao, Feba Sam, Nina DiPrimio, Zachary Parton, Hillary Tsang, Kausalya Murthy, Sangeetha Venkatraman Iyer, Joshua Mast, Tamy May Sharly Portillo Rodriguez, Madeleine Prangley
  • Publication number: 20210303050
    Abstract: Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Inventors: Eric Ching, Venkatraman Iyer
  • Patent number: 11113225
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Patent number: 11080212
    Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Patent number: 11061761
    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
  • Publication number: 20210182231
    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
  • Publication number: 20210117350
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 25, 2020
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20210097015
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Patent number: 10963415
    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
  • Patent number: 10931329
    Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
  • Publication number: 20210030721
    Abstract: The present disclosure relates generally to compounds and pharmaceutical compositions for increasing glycosylation and treating congenital disorders of glycosylation.
    Type: Application
    Filed: October 6, 2020
    Publication date: February 4, 2021
    Inventors: Ethan Oren Perlstein, Jessica Lao, Feba Sam, Nina DiPrimio, Zachary Parton, Hillary Tsang, Kausalya Murthy, Sangeetha Venkatraman Iyer, Joshua Mast, Tamy May Sharly Portillo Rodriguez, Madeleine Prangley
  • Patent number: 10909055
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • Publication number: 20200409896
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Patent number: 10868765
    Abstract: A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 15, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Bernd Sostawa, Martin Miller, Michael Rentschler, Venkatraman Iyer
  • Patent number: 10846258
    Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Zuoguo Wu, Mahesh Wagh
  • Publication number: 20200356502
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20200356496
    Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
    Type: Application
    Filed: March 30, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Publication number: 20200356436
    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
  • Publication number: 20200319957
    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
    Type: Application
    Filed: January 31, 2020
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu