Patents by Inventor Venkatraman Iyer
Venkatraman Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10931329Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.Type: GrantFiled: December 29, 2016Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Rahul R. Shah, William R. Halleck, Fulvio Spagna, Venkatraman Iyer
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Publication number: 20210030721Abstract: The present disclosure relates generally to compounds and pharmaceutical compositions for increasing glycosylation and treating congenital disorders of glycosylation.Type: ApplicationFiled: October 6, 2020Publication date: February 4, 2021Inventors: Ethan Oren Perlstein, Jessica Lao, Feba Sam, Nina DiPrimio, Zachary Parton, Hillary Tsang, Kausalya Murthy, Sangeetha Venkatraman Iyer, Joshua Mast, Tamy May Sharly Portillo Rodriguez, Madeleine Prangley
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Patent number: 10909055Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.Type: GrantFiled: July 29, 2019Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
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Publication number: 20200409896Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: June 5, 2020Publication date: December 31, 2020Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 10868765Abstract: A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.Type: GrantFiled: November 8, 2018Date of Patent: December 15, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bernd Sostawa, Martin Miller, Michael Rentschler, Venkatraman Iyer
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Patent number: 10846258Abstract: A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal on a particular one of the plurality of lanes of the physical link, where the stream signal is to identify a type of the data on the one or more data lanes, the type is one of a plurality of different types supported by the particular component, and the stream signal is encoded through voltage amplitude modulation on the particular lane.Type: GrantFiled: September 30, 2016Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, Zuoguo Wu, Mahesh Wagh
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Publication number: 20200356496Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.Type: ApplicationFiled: March 30, 2020Publication date: November 12, 2020Applicant: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
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Publication number: 20200356502Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20200356436Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Publication number: 20200319957Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: ApplicationFiled: January 31, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Patent number: 10795841Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.Type: GrantFiled: February 25, 2019Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren Jue, Sitaraman Iyer
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Publication number: 20200293480Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: February 26, 2020Publication date: September 17, 2020Applicant: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10747688Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.Type: GrantFiled: December 22, 2016Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Michelle Jen, Debendra Das Sharma, Venkatraman Iyer, Tao Liang
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Publication number: 20200244397Abstract: Data of different types are received on a plurality of data lanes of a physical link. Particular data is received on at least a portion of the plurality of data lanes, and a stream signal, corresponding to the particular data, is received on another of the lanes of the physical link, where the particular data is of a particular type different from other data previously sent on the plurality of data lanes. The stream signal includes a code component indicating that the particular data is of the particular type and a parity component for use in identifying whether a bit error is present in the stream signal.Type: ApplicationFiled: September 26, 2015Publication date: July 30, 2020Inventors: Venkatraman Iyer, Mahesh Wagh, Joon Teik HOR
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Patent number: 10712809Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.Type: GrantFiled: January 7, 2019Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Naveen Cherukuri, Jeffrey Wilcox, Venkatraman Iyer, Selim Bilgin, David S. Dunning, Robin Tim Frodsham, Theodore Z. Schoenborn, Sanjay Dabral
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Patent number: 10678736Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: September 25, 2015Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 10606774Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.Type: GrantFiled: December 21, 2017Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
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Patent number: 10599602Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: June 20, 2019Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Patent number: 10560081Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.Type: GrantFiled: June 26, 2017Date of Patent: February 11, 2020Assignee: Intel CorporationInventors: Mahesh Wagh, Zuoguo J. Wu, Venkatraman Iyer, Gerald S. Pasdast, Todd A. Hinck, David M. Lee, Narasimha R. Lanka
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Publication number: 20200043497Abstract: An electronic apparatus and method of controlling the electronic apparatus are provided. The electronic apparatus includes a communicator, a storage storing information on places wherein Internet of Things (IoT) devices are located, and a processor configured to, based on receiving a control signal for controlling an IoT device located in a specific place through the communicator, control the IoT device located in the specific place based on information on the place stored in the storage. The processor is further configured to receive motion information generated based on a motion of a wearable device from the wearable device, identify a place corresponding to the motion information, and store the identified place as information on a place of an IoT device located within a predetermined distance from the wearable device, in the storage.Type: ApplicationFiled: July 26, 2019Publication date: February 6, 2020Inventors: Seongil HAHM, Taejun KWON, Venkatraman IYER, Daesung AN