Patents by Inventor Venkatraman Iyer
Venkatraman Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11405127Abstract: Various embodiments relate to a wired local area network (WLAN) including a shared transmission medium (e.g., a 10SPE network). A method may include detecting an event in a WLAN including physical level collision avoidance (PLCA). The method may also include disabling a beacon of a first node operating as a master of the WLAN in response to the event. Further, the method may include enabling a second node to operate as the master of the WLAN.Type: GrantFiled: January 22, 2020Date of Patent: August 2, 2022Assignee: Microchip Technology IncorporatedInventors: Michael Rentschler, Martin Miller, Thorben Link, Venkatraman Iyer
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Patent number: 11398925Abstract: Disclosed embodiments relate, generally, to traffic shaping at a network segment having a shared bus. Some embodiments relate to performing aspects of the traffic shaping at a physical layer device. In some cases, transmit timeslot signaling may be tuned at a physical layer device to create transmit timeslots that are aligned with the traffic shaping profile.Type: GrantFiled: November 5, 2019Date of Patent: July 26, 2022Assignee: Microchip Technology IncorporatedInventors: Michael Rentschler, Venkatraman Iyer
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Patent number: 11386033Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: December 14, 2020Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11354264Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: February 25, 2021Date of Patent: June 7, 2022Assignee: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Publication number: 20220125766Abstract: The present disclosure relates generally to compounds and pharmaceutical compositions for increasing glycosylation and treating congenital disorders of glycosylation.Type: ApplicationFiled: September 29, 2021Publication date: April 28, 2022Inventors: Ethan Oren Perlstein, Jessica Lao, Feba Sam, Nina DiPrimio, Zachary Parton, Hillary Tsang, Kausalya Murthy, Sangeetha Venkatraman Iyer, Joshua Mast, Tamy May Sharly Portillo Rodriguez, Madeleine Prangley
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Patent number: 11307928Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: GrantFiled: July 24, 2020Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Publication number: 20220114122Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20220095377Abstract: Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Inventors: Venkatraman Iyer, Dixon Chen, John Junling Zang, Michael Rentschler
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Patent number: 11269793Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: GrantFiled: July 23, 2020Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20220052775Abstract: Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.Type: ApplicationFiled: October 28, 2021Publication date: February 17, 2022Inventors: Venkatraman Iyer, Dixon Chen, John Junling Zang, Shivanand I. Akkihal
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Patent number: 11197322Abstract: Various embodiments relate to wired local area networks. A method may include detecting, at a node in a wired local area network, at least one event. A physical layer device of the network node is configured to implement a physical level collision avoidance (PLCA) sublayer. The at least one event may include at least one of an amount of data stored in a first-in-first-out (FIFO) buffer of the node being at least a threshold amount, and a received packet being a precision time protocol (PTP) packet incurring variable delay. The method may further include emulating a collision at the node in response to the at least one detected event.Type: GrantFiled: April 8, 2020Date of Patent: December 7, 2021Assignee: Microchip Technology IncorporatedInventors: Venkatraman Iyer, Dixon Chen, John Junling Zang, Michael Rentschler
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Patent number: 11160794Abstract: The present disclosure relates generally to compounds and pharmaceutical compositions for increasing glycosylation and treating congenital disorders of glycosylation.Type: GrantFiled: October 6, 2020Date of Patent: November 2, 2021Assignee: Maggie's Pearl, LLCInventors: Ethan Oren Perlstein, Jessica Lao, Feba Sam, Nina DiPrimio, Zachary Parton, Hillary Tsang, Kausalya Murthy, Sangeetha Venkatraman Iyer, Joshua Mast, Tamy May Sharly Portillo Rodriguez, Madeleine Prangley
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Publication number: 20210303050Abstract: Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface.Type: ApplicationFiled: March 24, 2021Publication date: September 30, 2021Inventors: Eric Ching, Venkatraman Iyer
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Patent number: 11113225Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: June 5, 2020Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11080212Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.Type: GrantFiled: March 30, 2020Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
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Patent number: 11061761Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.Type: GrantFiled: January 31, 2020Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Venkatraman Iyer, Robert G. Blankenship, Mahesh Wagh, Zuoguo Wu
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Publication number: 20210182231Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Inventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee
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Publication number: 20210117350Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.Type: ApplicationFiled: December 25, 2020Publication date: April 22, 2021Applicant: Intel CorporationInventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
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Publication number: 20210097015Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 10963415Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.Type: GrantFiled: February 26, 2020Date of Patent: March 30, 2021Assignee: INTEL CORPORATIONInventors: Venkatraman Iyer, William R. Halleck, Rahul R. Shah, Eric Lee