Abstract: Integrated Bandwidth Latency Scheduler apparatus, method and system (collectively, IBLS) combines Fair Queuing and Priority Schedulers in a single stage to provide bandwidth fairness guarantees as well as latency prioritization. The IBLS includes a scheduler and process that dequeues packets from multiple queues in an order based upon an algorithm of the IBLS that arranges and dequeues those queues having the highest priority based on content therein. The IBLS also utilizes quotas and deficit counters to ensure that packets from each source receive their fair portion of the outgoing link bandwidth. To determine which first in first out queue an incoming data packet is placed, the enqueue agent utilized by the present invention classifies incoming packets based on the type of data included within the data packet, the source of the packet, the type of data flow, or another attribute of the packet, such as a header associated with the packet.

Abstract: A very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel. A very long instruction word contains a plurality of fields or issue slots for specifying which operations are to be performed by the functional units. Execution of an operation can be inhibited by a guard value specified in the issue slot. Instructions are dispatched in such a guarded VLIW architecture by routing one of a plurality of fields issued for a common functional unit based on the guard value. Thus, an instruction word may contain a greater number of issue slots than there are functional units.