Patents by Inventor Vijay Narayanan

Vijay Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistive switching memory stack for three-dimensional structure
    Patent number: 10270029
    Abstract: A resistive switching memory stack is provided. The resistive switching memory stack includes a bottom electrode, formed from one or more conductors. The resistive switching memory stack further includes an oxide layer, disposed over the bottom electrode, formed from an Atomic Layer Deposition (ALD) of one or more oxides. The resistive switching memory stack also includes a top electrode, disposed over the oxide layer, formed from the ALD of a plurality of metals into a metal layer stack. An oxygen vacancy concentration of the resistive switching memory stack is controlled by (i) a thickness of the plurality of metals forming the top electrode and (ii) a percentage of a particular one of the plurality of metals in the metal layer stack of the top electrode.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Vijay Narayanan, John Rozen
  • High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
    Patent number: 10262999
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Field effect transistor stack with tunable work function
    Patent number: 10249543
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Dual channel CMOS having common gate stacks
    Patent number: 10249540
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Shared metal gate stack with tunable work function
    Patent number: 10243055
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Dual channel CMOS having common gate stacks
    Patent number: 10229856
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • TAPERED METAL NITRIDE STRUCTURE
    Publication number: 20190067413
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Binary metal oxide based interlayer for high mobility channels
    Patent number: 10217834
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 26, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
    Patent number: 10217745
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Binary metal oxide based interlayer for high mobility channels
    Patent number: 10217835
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 26, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC.
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • SHARED METAL GATE STACK WITH TUNABLE WORK FUNCTION
    Publication number: 20190027572
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
    Type: Application
    Filed: September 24, 2018
    Publication date: January 24, 2019
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Process for preparing ?-damascone
    Patent number: 10150730
    Abstract: The present invention relates to a process for preparing 1-(2,6,6-trimethylcyclohex-2-en-1-yl)but-2-en-1-one, which comprises a) providing 6,10-dimethylundeca-1,5,9-trien-4-ol, b) oxidizing 6,10-dimethylundeca-1,5,9-trien-4-ol provided in step a) with an oxidizing agent in the presence of at least one organic nitroxyl radical, at least one nitrate compound and an inorganic solid to yield 6,10-dimethylundeca-1,5,9-trien-4-one, c) reacting the 6,10-dimethylundeca-1,5,9-trien-4-one obtained in step b) with an acid to yield 1-(2,6,6-trimethylcyclohex-2-en-1-yl)but-2-en-1-one.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: December 11, 2018
    Assignee: BASF SE
    Inventors: Stefan Rüdenauer, Thomas Fenlon, Shrirang Hindalekar, Nisha Pansare, Abhijeet Deb Roy, Vijay Narayanan Swaminathan
  • Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs
    Patent number: 10153201
    Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 11, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK SUNY POLYTECHNIC INSTITUTE
    Inventors: Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi, Tenko Yamashita
  • UNIFORM THRESHOLD VOLTAGE FOR NANOSHEET DEVICES
    Publication number: 20180350935
    Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.
    Type: Application
    Filed: July 20, 2018
    Publication date: December 6, 2018
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee, Vijay Narayanan, Koji Watanabe
  • Tapered metal nitride structure
    Patent number: 10147782
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • DUAL CHANNEL CMOS HAVING COMMON GATE STACKS
    Publication number: 20180337097
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Application
    Filed: May 16, 2017
    Publication date: November 22, 2018
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • DUAL CHANNEL CMOS HAVING COMMON GATE STACKS
    Publication number: 20180337098
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Application
    Filed: November 15, 2017
    Publication date: November 22, 2018
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • FIELD EFFECT TRANSISTOR GATE STACK
    Publication number: 20180330996
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • SELF-ALIGNED METAL GATE WITH POLY SILICIDE FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS
    Publication number: 20180331101
    Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Inventors: Brent A. Anderson, Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS
    Publication number: 20180308844
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 25, 2018
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen