Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

Abstract: Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.

Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.

Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.

Abstract: A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

Abstract: Disclosed herein are embodiments of an automated manufacturing system that is used to process multiple jobs in a product fabrication environment, where such processing comprises performing the same multiple consecutive process steps for each job and where each process step can be accomplished using one or more different available processing tools. The manufacturing system incorporates a unique run-time dispatch system. This dispatch system schedules the order in which jobs will be processed and further randomly assigns a particular combination of process steps and tools to each job in such a way that the processing tools are evenly distributed across the jobs. Ensuring even distribution of processing tools allows a statistical process control system to not only detect, for a given process step, product variability outside desired specifications, but also to efficiently de-convolve such product variability.

Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

Abstract: Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

Abstract: Disclosed herein are embodiments of an automated manufacturing system that is used to process multiple jobs in a product fabrication environment, where such processing comprises performing the same multiple consecutive process steps for each job and where each process step can be accomplished using one or more different available processing tools. The manufacturing system incorporates a unique run-time dispatch system. This dispatch system schedules the order in which jobs will be processed and further randomly assigns a particular combination of process steps and tools to each job in such a way that the processing tools are evenly distributed across the jobs. Ensuring even distribution of processing tools allows a statistical process control system to not only detect, for a given process step, product variability outside desired specifications, but also to efficiently de-convolve such product variability.

Abstract: A method of forming airgaps is provided where a blocking mask is applied to a substrate to shield a portion of the substrate from a beam of energy. After irradiation, the blocking mask is removed and a capping material is applied to the substrate. Alternatively, the capping material may be applied before irradiation. The capping material is perforated to allow an etchant to pass therethrough to the substrate below the capping material. The exposed portions of the substrate are removed from underneath the capping material by etching. The capping material is then sealed leaving sealed airgaps within the substrate.

Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Abstract: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.