Patents by Inventor Vincent J. McGahay
Vincent J. McGahay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6821890Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.Type: GrantFiled: May 7, 2001Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, Thomas H. Ivers, Joyce C. Liu, Henry A. Nye, III
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Publication number: 20040142565Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.Type: ApplicationFiled: October 16, 2003Publication date: July 22, 2004Inventors: Edward C. Cooney, Robert M. Geffken, Vincent J. McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
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Publication number: 20040129938Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.Type: ApplicationFiled: January 8, 2003Publication date: July 8, 2004Applicant: International Business Machines CorporationInventors: William F. Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Scott W. Crowder, Vincent J. McGahay, Sandra G. Malhotra, Charles R. Davis, Ronald D. Goldblatt, Brett H. Engel
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Publication number: 20040113278Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dalton, Sanjit K. Das, Brett H. Engel, Brian W. Herbst, Habib Hichri, Bernd E. Kastenmeier, Kelly Malone, Jeffrey R. Marino, Arthur Martin, Vincent J. McGahay, Ian D. Melville, Chandrasekhar Narayan, Kevin S. Petrarca, Richard P. Volant
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Patent number: 6727589Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: November 30, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6674168Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.Type: GrantFiled: January 21, 2003Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Robert M Geffken, Vincent J McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
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Publication number: 20030155655Abstract: An integrated circuit structure comprises a main dielectric layer having a top surface. A cavity having sidewalls is formed in the main dielectric layer. A liner is formed on the sidewalls of the cavity. A metal conductor such as copper is formed over the liner filling the lined cavity. A getter layer is formed in the structure which combines with oxygen/moisture to form inert reaction products thereof. The getter layer can be either a conductive material which can be included in the liner or a dielectric layer which can be formed on top of the main dielectric layer, buried in the main dielectric layer or below the main dielectric layer.Type: ApplicationFiled: February 20, 2002Publication date: August 21, 2003Applicant: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen M. Gates, Vincent J. McGahay
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Patent number: 6479884Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: June 29, 2001Date of Patent: November 12, 2002Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20020132471Abstract: The invention produces an integrated line/via interconnect structure comprising a high-modulus liner material that provides compression and back pressure, thus enhancing electromigration resistance and aiding heat dissipation.Type: ApplicationFiled: March 16, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Brett H. Engel, Vincent J. McGahay
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Patent number: 6387754Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.Type: GrantFiled: June 22, 2001Date of Patent: May 14, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Timothy J. Dalton, Andrew P. Cowley, Peter A. Emmi, Erdem Kaltalioglu, Vincent J. McGahay
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Patent number: 6348736Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.Type: GrantFiled: October 29, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, John P. Hummel, Joyce Liu, Rebecca Mih, Kamalesh Srivastava, Robert Cook, Stephen E. Greco
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Patent number: 6331481Abstract: The present invention relates to a method of integrating a low dielectric material such as DLC into a dual or single damascene wiring structure which contains a dielectric material having a dielectric constant of 4.0 or above. This integration is achieved in the present invention by employing a step of etchingback the high dielectric constant material to expose regions of in-laid wiring present in the single or dual damascene structure. Damascene wiring structures, single or dual, prepared using the method of the present invention are also provided herein.Type: GrantFiled: January 4, 1999Date of Patent: December 18, 2001Assignee: International Business Machines CorporationInventors: Anthony K. Stamper, Vincent J. McGahay
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Patent number: 6329280Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: May 13, 1999Date of Patent: December 11, 2001Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010036753Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.Type: ApplicationFiled: June 22, 2001Publication date: November 1, 2001Inventors: Timothy J. Dalton, Andrew P. Cowley, Peter A. Emmi, Erdem Kaltalioglu, Vincent J. McGahay
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Publication number: 20010036739Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: ApplicationFiled: June 29, 2001Publication date: November 1, 2001Inventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010023987Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.Type: ApplicationFiled: May 7, 2001Publication date: September 27, 2001Inventors: Vincent J. Mcgahay, Thomas H. Ivers, Joyce Liu, Henry A. Nye
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Patent number: 6278147Abstract: An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.Type: GrantFiled: January 18, 2000Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Andrew P. Cowley, Peter A. Emmi, Erdem Kaltalioglu, Vincent J. McGahay
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Patent number: 6271595Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium bitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.Type: GrantFiled: January 14, 1999Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, Thomas H. Ivers, Joyce C. Liu, Henry A. Nye, III
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Patent number: 6261945Abstract: A copper-interconnect, low-K dielectric integrated circuit has reduced corrosion of the interconnect when the crackstop next to the kerf is also used as the primacy barrier to oxygen diffusion through the dielectric, with corresponding elements of the crackstop being constructed simultaneously with the circuit interconnect elements; e.g. horizontal interconnect elements have a corresponding structure in the crackstop and vias between interconnect layers have corresponding structures in the crackstop.Type: GrantFiled: February 10, 2000Date of Patent: July 17, 2001Assignee: International Business Machines CorporationInventors: Henry A. Nye, III, Vincent J. McGahay, Kurt A. Tallman
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Patent number: 6221780Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: September 29, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava