Patents by Inventor Vincent J. McGahay
Vincent J. McGahay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080237800Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINESS CORPORATIONInventors: ANIL K. CHINTHAKINDI, Vincent J. McGahay
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Publication number: 20080224135Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: ApplicationFiled: May 28, 2008Publication date: September 18, 2008Inventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang, Conal Eugene Murray
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Publication number: 20080185684Abstract: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.Type: ApplicationFiled: April 7, 2008Publication date: August 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer Eshun, Vincent J. McGahay, Anthony K. Stamper, Kunal Vaed
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Patent number: 7405147Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.Type: GrantFiled: January 30, 2004Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7388224Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: GrantFiled: August 10, 2006Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Publication number: 20080132055Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.Type: ApplicationFiled: January 18, 2008Publication date: June 5, 2008Applicant: International Business Machines CorporationInventors: Son Van Nguyen, Michael Lane, Stephen M. Gates, Xiao H. Liu, Vincent J. McGahay, Sanjay C. Mehta, Thomas M. Shaw
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Patent number: 7345305Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.Type: GrantFiled: October 12, 2005Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Lynne Marie Gignac, Vincent J. McGahay, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Publication number: 20080064163Abstract: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.Type: ApplicationFiled: September 13, 2006Publication date: March 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer Eshun, Vincent J. McGahay, Anthony K. Stamper, Kunal Vaed
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Patent number: 7335980Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.Type: GrantFiled: November 4, 2004Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Michael Lane, Stephen M. Gates, Xiao H. Liu, Vincent J. McGahay, Sanjay C. Mehta, Thomas M. Shaw
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Patent number: 7253105Abstract: The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.Type: GrantFiled: February 22, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Christos D. Dimitrakopoulos, Stephen M. Gates, Vincent J. McGahay, Sanjay C. Mehta
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Patent number: 7253100Abstract: Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.Type: GrantFiled: November 17, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Ronald A. DellaGuardia, Daniel C. Edelstein, Habib Hichri, Vincent J. McGahay
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Patent number: 7214608Abstract: Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.Type: GrantFiled: July 29, 2004Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Peter E. Biolsi, Lawrence A. Clevenger, Habib Hichri, Bernd E. Kastenmeier, Michael W. Lane, Jeffrey R. Marino, Vincent J. McGahay, Theodorus E. Standaert
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Patent number: 7109093Abstract: Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.Type: GrantFiled: March 22, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Michael W. Lane, Vincent J. McGahay, Thomas M. Shaw, Anthony K. Stamper
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Patent number: 7098676Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.Type: GrantFiled: January 8, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: William F. Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Scott W. Crowder, Vincent J. McGahay, Sandra G. Malhotra, Charles R. Davis, Ronald D. Goldblatt, Brett H. Engel
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Patent number: 7098054Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.Type: GrantFiled: February 20, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Jason Paul Gill, Vincent J. McGahay, Paul Stephen McLaughlin, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 7067902Abstract: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.Type: GrantFiled: December 2, 2003Date of Patent: June 27, 2006Assignee: International Business Machines CorporationInventors: Habib Hichri, Xiao H. Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw
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Patent number: 6989282Abstract: A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.Type: GrantFiled: April 1, 2004Date of Patent: January 24, 2006Assignee: International Business Machines CorporationInventors: Ronald Gene Filippi, Lynne Marie Gignac, Vincent J. McGahay, Conal Eugene Murray, Hazara Singh Rathore, Thomas M. Shaw, Ping-Chuan Wang
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Patent number: 6982227Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.Type: GrantFiled: October 16, 2003Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Robert M. Geffken, Vincent J. McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Christy S. Tyberg, Elizabeth T. Webster
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Patent number: 6831363Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.Type: GrantFiled: December 12, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Sanjit K. Das, Brett H. Engel, Brian W. Herbst, Habib Hichri, Bernd E. Kastenmeier, Kelly Malone, Jeffrey R. Marino, Arthur Martin, Vincent J. McGahay, Ian D. Melville, Chandrasekhar Narayan, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20040245636Abstract: A method and structure for semiconductor structure includes a plurality of adjacent wiring levels, conductors within each of the wiring levels, and liners at least partially surrounding each of the conductors. The liners of adjacent wiring levels are made of different materials which have different etching characteristics and are selectively etchable with respect to one another. The liners can be tantalum, tungsten, etc. The liners surround at least three sides of the conductors. Each of the wiring levels has a first insulator layer which has a first dielectric material. The liners and the conductors are positioned within the first dielectric material. A second insulator layer has a second dielectric material over the first insulator layer. The first dielectric material has a lower dielectric constant than the second dielectric material. The first dielectric material can be silicon dioxide, fluorinated silicon dioxide (FSD), microporous glasses, etc.Type: ApplicationFiled: June 6, 2003Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Edward C Cooney, Robert M Geffken, Vincent J. McGahay, William T. Motsiff, Mark P. Murray, Amanda L. Piper, Anthony K. Stamper, David C. Thomas, Elizabeth T. Webster