Abstract: There is provided methods and apparatus for improving the accuracy of three-dimensional objects formed by additive manufacturing. By depositing or hardening build material within the interior of the layers in certain patterns, the stresses that lead to curl in the object can be isolated and controlled. Similarly, certain patterns for depositing or hardening the build material provide for reduced layer thicknesses to improve the sidewall quality of the object being formed. The patterns within the interior of the layers can include gaps or voids for particular layers being deposited or hardened, and the gaps or voids can be partially filled, fully filled, or not filled at all when subsequent layers are deposited or hardened. Accordingly, the accuracy of three-dimensional objects formed by additive manufacturing is improved.

Abstract: There are provided method and apparatus for the forming of three-dimensional objects in a layered fashion, wherein improvements are made to the support structure to improve the quality of the resulting three-dimensional objects. The support structure may include encapsulation along the interface boundary of the support-object interface to prevent or reduce the likelihood of separation of the build material, that forms the three-dimensional object, from the support material, that forms the support structure, or vice versa. The support structure may also or alternatively include both a porous support structure and a solid support structure to prevent or reduce the likelihood of, separation of the support structure from the build platform and to improve the quality of the down-facing surfaces of the three-dimensional object. Methods are also provided for selectively depositing the support material and build material and for encapsulating the interface boundary with support material.

Abstract: A system and method for packet processing are disclosed. The method may include performing using at least one processor, generating a DVB transport stream packet from a DSS transport stream packet. The generation may include mapping a prefix portion of a DSS transport stream packet into a header portion of the DVB transport stream packet comprising an inserted adaptation field. The inserted adaptation field may increase a size of the header portion of the DVB transport stream packet, and may decrease a size of a payload portion of the of the DVB transport stream. The generation may also include mapping a payload portion of the DSS transport stream packet into the payload portion of the DVB transport stream packet comprising the decreased size. The adaptation field may be at least fifty six (56) bytes in size.

Abstract: Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: Selectively providing LC overdrive by determining a relative noise level between a current video frame and a previous video frame and overdriving the current video frame based upon the determined relative noise level.

Abstract: Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

Abstract: Aspects of the method and system for converting a DSS transport stream to a DVB transport stream include encapsulating at least a prefix portion and a payload portion of a DSS transport packet into at least a header portion and a payload portion of a DVB transport packet. At least a portion of the prefix portion and the payload portion of the DSS transport packet may be mapped into at least a portion of the header portion and the payload portion of the DVB transport packet. At least a portion of the payload of the DSS transport packet may be aligned with at least a portion of the payload portion of the DVB transport packet.

Abstract: Aspects of the method and system for converting a DSS transport stream to a DVB transport stream include encapsulating at least a prefix portion and a payload portion of a DSS transport packet into at least a header portion and a payload portion of a DVB transport packet. At least a portion of the prefix portion and the payload portion of the DSS transport packet may be mapped into at least a portion of the header portion and the payload portion of the DVB transport packet. At least a portion of the payload of the DSS transport packet may be aligned with at least a portion of the payload portion of the DVB transport packet.

Abstract: Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Abstract: The present invention is directed to a new bonding pad structure that includes a copper pad and a pad surface finish comprising multiple layers of solder. The multiple layers of solder include at least a layer of eutectic solder (or a layer of pure-Sn solder) covering the copper pad and a layer of high-Pb solder covering the layer of eutectic solder (or the layer of pure-Sn solder). Since the layer of high-Pb solder is significantly thicker than the eutectic solder layer (or the layer of pure-Sn solder), there is insufficient tin supply in the eutectic solder (or the layer of pure-Sn solder) for forming a thick Cu/Sn intermetallic layer on the copper pad. Instead, a thin Cu/Sn intermetallic layer is formed on the copper pad and there is less likelihood of forming a crack in the thin Cu/Sn intermetallic layer.

Abstract: Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Abstract: A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate Fs. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value Su and a lower value Sl so that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: A system may include a number of detectors and a processor. Each detector may be arranged to receive a different number of N leading bits. Each detector may output an affirmative feedback bit if the different number of N leading bits matches a respective predetermined pattern. The processor may provide the N leading bits to the number of detectors and may receive a corresponding number of feedback bits. The processor may also determine an Exponential Golomb code number based on the number of feedback bits.

Abstract: A reduced memory method, apparatus, and system suitable for implementation in Liquid Crystal Display (LCDs) that reduces a pixel element response time thereby enabling the display of high quality fast motion images thereupon. As a method of generating an overdrive pixel value in an LCD device, a predicted pixel value is compressed and stored. The stored compressed pixel value is then retrieved and decompressed as a start pixel value. An overdrive pixel value based upon a target pixel value and the start pixel value such that the overdrive pixel value enables a pixel to reach the target pixel value within a single frame period.

Abstract: Selectively providing LC overdrive by determining a relative noise level between a current video frame and a previous video frame and overdriving the current video frame based upon the determined relative noise level.

Abstract: Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.

Abstract: Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

Abstract: A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.