Abstract: A method, system and apparatus for detecting a sub-pixel pair susceptible of producing a flicker event in an image from a video signal source displayed on a liquid crystal display (LCD) unit is described. A two dimensional flicker pattern analysis is performed on a selected group of sub-pixels some of which are included in a first plurality of sub-pixels that includes a first current sub-pixel and a first next sub-pixel included in a first video frameline and a remainder of which are included in a second plurality of sub-pixels included in a second video frameline that is received, in real time, from the video signal source that includes a second current sub-pixel and a second current sub-pixel.

Abstract: A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

Abstract: Device modules with pins and methods for making device modules with pins are disclosed. One embodiment is directed to a method including forming a polymeric circuit structure having a first side and a second side on a substrate. The formed first side is adjacent to the substrate. A pin is bonded to the second side of the polymeric circuit structure. At least a portion of the substrate is removed to expose at least a portion of the first side of the polymeric circuit structure, and a device is mounted on the first side of the polymeric circuit structure.

Abstract: Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed.

Abstract: A method for forming a multilayer circuit substrate is disclosed. Preferably, a multilayer circuit substrate precursor is formed using a build up process. The multilayer circuit substrate precursor comprises an internal conductive post, an internal conductive layer coupled to one end of the conductive post, and an dielectric layer disposed around the conductive post. The multilayer circuit substrate precursor and the conductive post are cut to form a side electrical contact structure from the cut post.

Abstract: A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump.

Abstract: Methods for forming multilayer circuit structures are disclosed. In some embodiments, conductive layers, dielectric layers and conductive posts can be formed on both sides of a circuitized core structure. The conductive posts are disposed in the dielectric layers and can be stacked to form a generally vertical conduction pathway which passes at least partially through a multilayer circuit structure. The formed multilayer circuit structures can occupy less space than corresponding multilayer circuit structures with stacked via structures.

Abstract: An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveduide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. A method for producing an optoreflective structure comprising providing a substrate supporting a first cladding layer having a first planar cladding surface; disposing a waveguide material on the first cladding layer; and forming on the waveguide material a second cladding layer having a second planar cladding surface.

Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.

Abstract: A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.

Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

Abstract: A method of fabricating a substrate having a conductive layer on opposing sides, with the conductive layers interconnected by a conductive via. The inventive method uses a dielectric substrate having a conductive layer deposited or laminated onto one or both of the substrate's opposing surfaces. For the situation of a metal layer on one side of the substrate, a laser drill is used to drill blind vias through the dielectric, stopping at the substrate/conductive layer interface. An electrolytic plating process is used to fill the via by establishing an electrical connection to the conductive layer. A second conductive layer may be deposited or laminated to the other surface of the substrate. If the starting structure has a conductive layer on both sides of the substrate, the drill is controlled to bore through the upper conductive layer at a comparatively high power and then continue at a lower power through the substrate.

Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core.

Abstract: A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.

Abstract: An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.

Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink).

Abstract: An interposer structure permits a differential transverse displacement of contact pads on opposite sides of the interposer to reduce thermal stresses when the interposer is bonded to contact pads of a chip and a substrate with different thermal coefficients of expansion. The effective elasticity of the interposer between top and bottom contact pads of the interposer is facilitated by perforations which define flap-like regions. A flexible trace couples top contact pads to bottom contact pads through a via while permitting substantial transverse relative displacement of the top and bottom contact pads in flap-like regions.