Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

Abstract: An optoreflective structure for reflecting an optical signal following a path defined by an optical waveguide comprising a first cladding layer having a first planar cladding surface; a waveguide disposed on the first cladding layer; and a second cladding layer disposed on the waveguide and having a second planar cladding surface. The first cladding layer, the second cladding layer and the waveguide terminate in a generally dove-tailed structure having a beveled planar surface. An optoreflector is disposed on the beveled planar surface for a changing direction of an optical signal passing through the waveguide. Methods of producing the optoreflective structure are disclosed.

Abstract: Provided are flip chip device assembly methods that integrate the solder joining and underfill operations of the assembly process. Solder joining of the die and substrate and curing of the underfill material between the die and substrate is accomplished in the same heating and cooling operation. As a result, the coefficient of thermal expansion (CTE) mismatch stresses incurred prior to application and curing of underfill by a device packaged according to the conventional technique having a separate heating and cooling operation following solder joining, are avoided. These stresses are of particular concern in smaller device size technologies (e.g., 0.13 microns and smaller) using low k dielectrics and large die sizes due the difference in CTP between the die and substrate.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: Aspects of the method and system for converting a DSS transport stream to a DVB transport stream include encapsulating at least a prefix portion and a payload portion of a DSS transport packet into at least a header portion and a payload portion of a DVB transport packet. At least a portion of the prefix portion and the payload portion of the DSS transport packet may be mapped into at least a portion of the header portion and the payload portion of the DVB transport packet. At least a portion of the payload of the DSS transport packet may be aligned with at least a portion of the payload portion of the DVB transport packet.

Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.

Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Abstract: A method, system and apparatus for detecting a sub-pixel pair susceptible of producing a flicker event in an image from a video signal source displayed on a liquid crystal display (LCD) unit is described. A two dimensional flicker pattern analysis is performed on a selected group of sub-pixels some of which are included in a first plurality of sub-pixels that includes a first current sub-pixel and a first next sub-pixel included in a first video frameline and a remainder of which are included in a second plurality of sub-pixels included in a second video frameline that is received, in real time, from the video signal source that includes a second current sub-pixel and a second current sub-pixel.

Abstract: A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.

Abstract: Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Abstract: Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.

Abstract: An optical apparatus including an optical substrate having an embedded waveguide and an optical device adapted to receive light transmitted from an end of the waveguide. The optical apparatus includes a coupling structure for coupling the optical device to the substrate. The coupling structure has a thin metallic layer with an aperture. At least a portion of the optical device is disposed in the aperture. A method for making an optical apparatus comprising forming an optical substrate having a waveguide embedded therein; depositing a metal layer over an end of the waveguide; and depositing a polymeric layer over the metal layer. An aperture is formed in the metal layer and in the polymeric layer by removing a portion of the metal layer and a portion of the polymeric layer disposed over the end of the waveguide.

Abstract: A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

Abstract: A method of fabricating a multilayer interconnected substrate is disclosed. In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface. A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate. A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate. The blind via site is filled with a conductive material by an electrolytic plating process.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.

Abstract: Unique Huffman codes are generated with each being associated with a symbol. The unique codes are grouped according to a property of the unique codes such as length. The segments of a data stream to be decoded are compared with the grouped unique codes. Each segment has the same property as the grouped unique codes being compared with.

Abstract: A system and a method for avoiding waiting repair analysis for a semiconductor testing equipment are disclosed. The semiconductor testing equipment directly executes next functional test after transferring previous test data regardless of if repair analysis is completed or not. A repair analysis apparatus has a pre-analysis storage device with a larger capacity than the test storage device of the semiconductor testing equipment for off-line repair analysis, so that the semiconductor test is efficiently improved.

Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.

Abstract: A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump.