Patents by Inventor Vineet Goel

Vineet Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190005604
    Abstract: A stage of a graphics pipeline in a graphics processing unit (GPU) detects an interrupt concurrently with the stage processing primitives in a first bin that represents a first portion of a first frame generated by a first application. The stage forwards a completed portion of the primitives to a subsequent stage of the graphics pipeline in response to the interrupt. The stage diverts a second bin that represents a second portion of the first frame from the stage to a memory in response to the interrupt. The stage processes primitives in a third bin that represents a portion of a second frame generated by a second application subsequent to diverting the second bin to the memory. The stage can then retrieve the second bin from the memory in response to the stage completing processing of the primitives in the third bin for additional processing.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Anirudh R. ACHARYA, Michael MANTOR, Vineet GOEL, Swapnil SAKHARSHETE
  • Publication number: 20180293761
    Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
  • Patent number: 10096147
    Abstract: In an example, a method for rendering a 3-D scene of graphical data into a 2-D scene may include dividing 2-D space used to represent the 3-D scene from a viewpoint into a plurality of tiles. The 3-D scene may include a plurality of primitives. The method may include generating visibility information for a first tile of the plurality of tiles. The method may include modifying the visibility information for the first tile to generate modified visibility information for the first tile. The method may include generating the 2-D scene using the modified visibility information for the first tile.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Ruijin Wu, Young In Yeo
  • Patent number: 9842376
    Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Anirudh Rajendra Acharya, Gang Zhong, Vineet Goel
  • Publication number: 20170323327
    Abstract: The SYNTHETIC CONTROL GENERATION AND CAMPAIGN IMPACT ASSESSMENT APPARATUSES, METHODS AND SYSTEMS (“SCG”) provides a platform that, in various embodiments, is configurable to evaluate efficacy and/or return on investment of advertising and/or other media campaigns and/or to recommend actions for improvement thereof. In some implementations, multi-faceted campaigns of media and/or advertising behavior (e.g., including one or more of: internet advertising, television advertising, radio advertising, print advertising, social media publication, product placement, and/or the like) may be considered as a whole in relation to global metric behaviors and/or patterns in order to evaluate the efficacy and/or return on investment associated with the campaign as a whole.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 9, 2017
    Inventors: Sejal Pachisia, Vineet Goel, Jen Liu, John Stockton, Arnau Tibau-Puig
  • Patent number: 9805495
    Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Juraj Obert, Tao Wang, Vineet Goel
  • Publication number: 20170293995
    Abstract: A graphics processing unit (GPU) may rasterize a primitive into a plurality of samples, wherein vertices of the primitive are associated with VRS parameters. The GPU may determine a VRS quality group that comprises one or more sub regions of the plurality of samples based at least in part on the VRS parameters. The GPU may fragment shade a VRS tile that represents the VRS quality group, wherein the VRS tile comprises fewer samples than the VRS quality group. The GPU may amplify the stored VRS tile into shaded fragments that correspond to the VRS quality group.
    Type: Application
    Filed: February 16, 2017
    Publication date: October 12, 2017
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Maurice Franklin Ribble, Andrew Evan Gruber
  • Patent number: 9779534
    Abstract: In an example, rendering graphics data includes determining, with a graphics processing unit (GPU), a texture offset for a current segment of a plurality of ordered segments of a dashed line, where the texture offset for the current segment of the plurality of ordered segments is based on an accumulation of lengths of segments that precede the current segment in the order, and pixel shading the current segment including applying the texture offset to determine a location of the current segment.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20170263039
    Abstract: In an example, a method for rendering a 3-D scene of graphical data into a 2-D scene may include dividing 2-D space used to represent the 3-D scene from a viewpoint into a plurality of tiles. The 3-D scene may include a plurality of primitives. The method may include generating visibility information for a first tile of the plurality of tiles. The method may include modifying the visibility information for the first tile to generate modified visibility information for the first tile. The method may include generating the 2-D scene using the modified visibility information for the first tile.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 14, 2017
    Inventors: Vineet Goel, Ruijin Wu, Young In Yeo
  • Publication number: 20170249771
    Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Juraj Obert, Tao Wang, Vineet Goel
  • Publication number: 20170243375
    Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
  • Publication number: 20170221173
    Abstract: A graphics processing unit (GPU) may dispatch a first set of commands for execution on one or more processing units of the GPU. The GPU may receive notification from a host device indicating that a second set of commands are ready to execute on the GPU. In response, the GPU may issue a first preemption command at a first preemption granularity to the one or more processing units. In response to the GPU failing to preempt execution of the first set of commands within an elapsed time period after issuing the first preemption command, the GPU may issue a second preemption command at a second preemption granularity to the one or more processing units, where the second preemption granularity is finer-grained than the first preemption granularity.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Anirudh Rajendra Acharya, Alexei Vladimirovich Bourd, David Rigel Garcia Garcia, Milind Nilkanth Nemlekar, Vineet Goel
  • Patent number: 9697640
    Abstract: At least one processor may organize a plurality of primitives in a hierarchical data structure. The at least one processor may rasterize a plurality of bounding volumes associated with non-root nodes of the hierarchical data structure to an off-screen render target. The at least one processor may determine a bounding volume that is intersected by a ray out of the plurality of bounding volumes. The at least one processor may determine a non-root node of the hierarchical data structure that is associated with the bounding volume as a start node in the hierarchical data structure to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine the primitive that is intersected by the ray.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: July 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Juraj Obert, Vineet Goel, Ouns Mouri
  • Patent number: 9679347
    Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chunhui Mei, Vineet Goel, Donghyun Kim
  • Patent number: 9665975
    Abstract: This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: May 30, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Donghyun Kim, Gang Zhong
  • Patent number: 9659341
    Abstract: A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Javier Ignacio Girado, Jay Chunsup Yun, Vineet Goel
  • Patent number: 9646359
    Abstract: An example method of filtering in a graphics processing unit (GPU) may include storing, by a texture engine of the GPU, filter coefficients of a filter as a texture memory object (TMO) in a texture cache of the GPU in response to a first instruction. The method may include retrieving, by the texture engine, filter coefficients from the texture cache in response to a second instruction. The method may include storing, by the texture engine, pixel data in the texture cache of the GPU in response to the second instruction. The pixel data may include one or more pixel values. The method may include filtering, by the texture engine, the pixel data stored in the texture cache using the retrieved filter coefficients.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 9, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Elina Kamenetskaya, Javier Ignacio Girado, Liang Li, Jay Chunsup Yun, Vineet Goel
  • Patent number: 9626762
    Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chunhui Mei, Tao Wang, Young In Yeo, Vineet Goel
  • Patent number: 9619853
    Abstract: This disclosure is directed to techniques for performing GPU-accelerated path rendering. A GPU is described that is configured to receive data indicative of a path segment of a path to be rendered, tessellate the path segment into a plurality of primitives, and render at least one of a fill area and a stroke area for the path segment based on the plurality of primitives. The techniques of this disclosure may be used to improve the performance of path rendering operations, to reduce memory bandwidth requirements needed to perform path rendering operations, and/or to reduce the memory footprint needed to perform path rendering operations.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20170091895
    Abstract: Techniques are described with respect to preemption in which a graphics processing unit (GPU) may execute a first set of commands in response to receiving a draw call, the draw call defining a plurality of primitives that are to be rendered by the first set of commands, receive a preemption notification during execution of the first set of commands, and preempt the execution of the first set of commands, prior to completing the execution of the first set of commands to render the plurality of primitives of the draw call, for executing a second set of commands.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 30, 2017
    Inventors: Anirudh Rajendra Acharya, Gang Zhong, Vineet Goel